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    11.
    发明专利
    未知

    公开(公告)号：DE69211447D1

    公开(公告)日：1996-07-18

    申请号：DE69211447

    申请日：1992-07-02

    Applicant: IBM

    Inventor： CHOI SUNG MIN ,  LUMELSKY LEON ,  PEEVERS ALAN WESLEY ,  PITTAS JOHN LOUIS

    IPC: G06T9/00 ,  G09G5/02 ,  G09G5/04 ,  G09G5/36 ,  H04N1/41 ,  G09G5/06

    Abstract: A display system is described which includes storage for receiving a compressed pixel image manifesting at least a pair of encoded colors and a bit MASK that defines which pixels of a pixel subset of the pixel image receive one of the colors. The system comprises a plurality of memory modules (34). The pixels in the subset are interleaved in the memory modules. A generator is provided for applying signals to cause data to be written into each of modules in parallel. Register means are provided for applying data manifesting the encoded colors to the modules. Control apparatus is responsive to the MASK bits for controlling the generator to write the encoded color data, in parallel and in a single memory cycle, into all pixel positions of the subset that are designated for the color(s) by MASK bit position values.

    14.
    发明专利
    未知

    公开(公告)号：DE69225538T2

    公开(公告)日：1999-02-04

    申请号：DE69225538

    申请日：1992-07-03

    Applicant: IBM

    Inventor： CHOI SUNG MIN ,  LUMELSKY LEON ,  PEEVERS ALAN WESLEY ,  PITTAS JOHN LOUIS

    IPC: G09G5/00 ,  G06F12/00 ,  G09G5/02 ,  G09G5/14 ,  G09G5/36 ,  G09G5/39 ,  G09G5/391 ,  G09G5/395 ,  H04N7/01

    Abstract: An image display system (10) includes an image buffer (20,22) having a plurality of addressable locations for storing image pixel data. The system further includes circuitry (24,34,36) coupled to an output of the image buffer for converting image pixel data read therefrom to electrical signals for driving an image display (18). The circuitry is responsive to signals generated by an image display controller (16) for generating one of a plurality of different timing formats for the electrical signals for driving an image display having a specified display resolution. The apparatus further includes circuitry (40,42) for configuring the image buffer in accordance with the specified display resolution. The image buffer is configurable, by example, as two, 2048 location by 1024 location by 24-bit buffers and one 2048 location by 1024 location by 16-bit buffer; or as two, 2048 location by 2048 location by 24-bit buffers and one 2048 location by 2048 location by 16-bit buffer. Each of the 24-bit buffers store R,G,B pixel data and the 16-bit buffers each store a color index (CI) value and an associated window identifier (WID) value. Circuitry at the output of the image buffer decodes CI and WID values into R,G,B pixel data and a Key value specifying pixel mixing.

    15.
    发明专利
    未知

    公开(公告)号：DE69211447T2

    公开(公告)日：1996-12-05

    申请号：DE69211447

    申请日：1992-07-02

    Applicant: IBM

    Inventor： CHOI SUNG MIN ,  LUMELSKY LEON ,  PEEVERS ALAN WESLEY ,  PITTAS JOHN LOUIS

    IPC: G06T9/00 ,  G09G5/02 ,  G09G5/04 ,  G09G5/36 ,  H04N1/41 ,  G09G5/06

    Abstract: A display system is described which includes storage for receiving a compressed pixel image manifesting at least a pair of encoded colors and a bit MASK that defines which pixels of a pixel subset of the pixel image receive one of the colors. The system comprises a plurality of memory modules (34). The pixels in the subset are interleaved in the memory modules. A generator is provided for applying signals to cause data to be written into each of modules in parallel. Register means are provided for applying data manifesting the encoded colors to the modules. Control apparatus is responsive to the MASK bits for controlling the generator to write the encoded color data, in parallel and in a single memory cycle, into all pixel positions of the subset that are designated for the color(s) by MASK bit position values.

    16.
    发明专利
    未知

    公开(公告)号：DE69015536D1

    公开(公告)日：1995-02-09

    申请号：DE69015536

    申请日：1990-06-05

    Applicant: IBM

    Inventor： LUMELSKY LEON ,  PEEVERS ALAN W ,  CHOI SUNG MIN

    IPC: H04N5/66 ,  G06T3/40 ,  G09G5/00 ,  G09G5/02 ,  G09G5/14 ,  G09G5/36 ,  H04N1/393 ,  H04N5/262 ,  H04N7/01 ,  H04N3/22 ,  G06T3/60 ,  G09G1/00

    Abstract: A video pixel presentation rate expansion circuit is provided for use with a high-resolution display system. The overall display system includes a high-resolution monitor, a computer for providing control signals, including a high-resolution frame buffer for storing computer graphics and TV video images and reading out said video data at a rate controlled by said control signals and providing said data with a high-resolution monitor for display. The expansion circuit of the present invention comprises means responsive to an expansion pattern generated by the computer for changing the time base of the video pixel data read out of said frame buffer. Circuit includes means responsive to said expansion pattern for selectively repeating predetermined scan lines of said video display and for selectively repeating certain pixel along a given scan line to match the time base of the video data read out of said frame buffer to the time base of said high-resolution monitor. According to a preferred embodiment of the invention the expansion circuit functions to modify the controi signals which controls the read-out of the frame buffer in a predetermined fashion without any additional video buffer storage means. In the simplest form of the invention the additional circuitry required comprises only two registers for holding the generated expansion patterns in the horizontal and vertical direction and two shift registers for receiving these patterns and processing same to alter the frame buffer clocks to achieve replication of predetermined lines and pixels as determined from the said expansion pattern.

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