公开(公告)号：GB2510768B

公开(公告)日：2016-01-06

申请号：GB201409117

申请日：2012-10-16

Applicant: IBM

Inventor： BANGSARUNTIP SARUNYA ,  COHEN GUY M ,  SLEIGHT JEFFREY W

IPC: H01L21/336 ,  B82Y10/00 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A field effect transistor device includes a nanowire, a gate stack comprising a gate dielectric layer disposed on the nanowire, a gate conductor layer disposed on the dielectric layer and a substrate, and an active region including a sidewall contact portion disposed on the substrate adjacent to the gate stack, the side wall contact portion is electrically in contact with the nanowire.

公开(公告)号：GB2510768A

公开(公告)日：2014-08-13

申请号：GB201409117

申请日：2012-10-16

Applicant: IBM

Inventor： BANGSARUNTIP SARUNYA ,  COHEN GUY M ,  SLEIGHT JEFFREY W

IPC: H01L21/336 ,  B82Y10/00 ,  H01L21/8234 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

Abstract: A method for forming a field effect transistor device includes forming a nanowire suspended above a substrate, forming a dummy gate stack on a portion of the substrate and around a portion of the nanowire, removing exposed portions of the nanowire, epitaxially growing nanowire extension portions from exposed portions of the nanowire, depositing a layer of semiconductor material over exposed portions of the substrate, the dummy gate stack and the nanowire extension portions, and removing portions of the semiconductor material to form sidewall contact regions arranged adjacent to the dummy gate stack and contacting the nanowire extension portions.

公开(公告)号：DE102021130641A1

公开(公告)日：2022-06-23

申请号：DE102021130641

申请日：2021-11-23

Applicant: IBM

Inventor： COHEN GUY M ,  ANDO TAKASHI ,  GONG NANBO

IPC: H01L45/00 ,  H01L27/24

Abstract: Ein einstellbares nichtflüchtiges resistives Element, wobei die Leitfähigkeit der Einheit durch Ändern der Länge eines Kontakts zwischen einem Phasenwechselmaterial und einem resistiven Liner moduliert wird. Indem die Kontaktlänge so gewählt wird, dass sie geringer als die Übertragungslänge ist, wird eine lineare Modulation der Leitfähigkeit erreicht.

公开(公告)号：CA2642875C

公开(公告)日：2015-09-22

申请号：CA2642875

申请日：2007-03-08

Applicant: IBM

Inventor： COHEN GUY M ,  HAMANN HENDRIK F

IPC: G01Q70/12 ,  G01Q70/16 ,  B81C99/00 ,  B82Y40/00 ,  G01Q60/22 ,  G01Q60/38 ,  G01Q70/06

Abstract: A scanning probe where the micromachined pyramid tip is extended by the growth of an epitaxial nanowire from the top portion of the tip is disclosed. A metallic particle, such as gold, may terminate the nanowire to realize an apertureless near-field optical microscope probe.

公开(公告)号：DE102012224274A1

公开(公告)日：2013-07-11

申请号：DE102012224274

申请日：2012-12-21

Applicant: IBM

Inventor： BANGSARUNTIP SARUNYA ,  COHEN GUY M ,  MAJUMDAR AMLAN ,  SLEIGHT JEFFREY W

IPC: H01L29/788 ,  B82Y10/00 ,  B82Y40/00 ,  H01L27/115 ,  H01L29/792

Abstract: Ein Floating-Gate-Transistor, eine Speicherzelle und ein Verfahren zum Fertigen einer Einheit. Der Floating-Gate-Transistor beinhaltet einen oder mehrere Gategesteuerte Drähte, die eine im Wesentlichen zylindrische Form aufweisen. Der Floating-Gate-Transistor beinhaltet eine erste Gate-Dielektrikumschicht, die die Gate-gesteuerten Drähte zumindest teilweise bedeckt. Der Floating-Gate-Transistor beinhaltet des Weiteren eine Vielzahl von Gate-Kristallen, die unzusammenhängend auf der ersten Gate-Dielektrikumschicht angeordnet sind. Der Floating-Gate-Transistor beinhaltet außerdem eine zweite Gate-Dielektrikumschicht, die die Vielzahl von Gate-Kristallen und die erste Gate-Dielektrikumschicht bedeckt.

公开(公告)号：DE60331473D1

公开(公告)日：2010-04-08

申请号：DE60331473

申请日：2003-12-02

Applicant: IBM

Inventor： COHEN GUY M ,  CHRISTIANSEN SILKE H

IPC: H01L21/20 ,  H01L21/762

Abstract: A method for fabricating a strained Si layer on insulator, a structure of the strained Si layer on insulator, and electronic systems comprising such layers are disclosed. The method comprises the steps of forming epitaxially a relaxed SiGe layer on top of a Si layer on insulator; transforming the crystalline Si layer and the lower portion of the crystalline relaxed SiGe layer into an amorphous material state by ion implantation; and re-crystallizing the amorphous material from the crystalline top portion of the SiGe layer. The larger lattice constant of the SiGe seed layer forces a tensile strain in the Si layer.

公开(公告)号：AU2003297627A1

公开(公告)日：2004-07-29

申请号：AU2003297627

申请日：2003-12-02

Applicant: IBM

Inventor： CHRISTIANSEN SILKE H ,  COHEN GUY M

IPC: H01L21/20 ,  H01L21/762

Abstract: A method for fabricating a strained Si layer on insulator, a structure of the strained Si layer on insulator, and electronic systems comprising such layers are disclosed. The method comprises the steps of forming epitaxially a relaxed SiGe layer on top of a Si layer on insulator; transforming the crystalline Si layer and the lower portion of the crystalline relaxed SiGe layer into an amorphous material state by ion implantation; and re-crystallizing the amorphous material from the crystalline top portion of the SiGe layer. The larger lattice constant of the SiGe seed layer forces a tensile strain in the Si layer.