公开(公告)号：DE1226626B

公开(公告)日：1966-10-13

申请号：DEJ0024891

申请日：1963-12-10

Applicant: IBM

Inventor： CHOMICKI JOHN S ,  CRITCHLOW DALE L

IPC: G06F13/38 ,  H03M1/00 ,  H04J99/00 ,  H04L5/04 ,  H04L7/027 ,  H04L25/48

Abstract: 996,409. Telegraphy; multiplex pulse code signalling. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 21, 1963 [Dec. 18, 1962], No. 45925/63. Drawings to Specification. Headings H4L and H4P. In a data receiver to counteract drift in the clamping circuit that occurs when the data has one value for some time a D.C. feed-back path is provided from the output of the receiver to the input. In the embodiment described two binary messages are transmitted as a single 4-level message by adding one to the other doubled in amplitude. This message is preceded by a signal which causes a clamp in the receiver to place the received data at the correct level. The data is fed to threshold circuits which provide three signals indicative of the level of the data. These signals are fed to logic circuitry to derive output signals the equivalent of the original two binary messages. The outputs from the logic are combined to give a four-level signal which acts in the D.C. feed-back loop to stabilize the D.C. level at the receiver input.

公开(公告)号：CA888984A

公开(公告)日：1971-12-21

申请号：CA888984D

Applicant: IBM

Inventor： SCHUSTER STANLEY E ,  CRITCHLOW DALE L

公开(公告)号：CA807236A

公开(公告)日：1969-02-25

申请号：CA807236D

Applicant: IBM

Inventor： CRITCHLOW DALE L ,  DENNARD ROBERT H

公开(公告)号：CA734062A

公开(公告)日：1966-05-10

申请号：CA734062D

Applicant: IBM

Inventor： CRITCHLOW DALE L

公开(公告)号：CA733660A

公开(公告)日：1966-05-03

申请号：CA733660D

Applicant: IBM

Inventor： HOPNER EMIL ,  FUNK HOWARD L ,  CRITCHLOW DALE L

公开(公告)号：DE3883185T2

公开(公告)日：1994-03-17

申请号：DE3883185

申请日：1988-11-30

Applicant: IBM

Inventor： CRITCHLOW DALE L ,  DEBROSSE JOHN K ,  MOHLER RICK L ,  NOBLE WENDELL P ,  PARRIES PAUL C

IPC: H01L21/28 ,  H01L21/74 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L21/82

公开(公告)号：CA802452A

公开(公告)日：1968-12-24

申请号：CA802452D

Applicant: IBM

Inventor： CRITCHLOW DALE L

公开(公告)号：DE1238966B

公开(公告)日：1967-04-20

申请号：DEJ0028538

申请日：1965-07-08

Applicant: IBM

Inventor： CRITCHLOW DALE L

IPC: H03D1/24

公开(公告)号：DE1228657B

公开(公告)日：1966-11-17

申请号：DEJ0024911

申请日：1963-12-12

Applicant: IBM

Inventor： CRITCHLOW DALE L ,  DENNARD ROBERT H

IPC: H03D1/24 ,  H04B1/68 ,  H04L27/02

Abstract: 1,031,596. Vestigial sideband transmission systems. INTERNATIONAL BUSINESS MACHINES CORPORATION. Nov. 21, 1963 [Dec. 18, 1962], No. 45929/63. Heading H3R. In a vestigial side-band suppressed carrier system for transmitting data signals and particularly in such a system where a repetitive data pattern is transmitted which contains no D.C. or low frequency A.C. components, the difficulty of reconstituting the carrier for synchronous detection at the receiver is overcome by adding either a D.C. signal or a low frequency A.C. signal to the data signal before application to a balanced modulator whereby either a small amount of carrier or two side-band signals equally disposed on either side of the carrier position are transmitted. The data signals are applied via unit 5, Fig. 2, and L.P. filter 6 to a balanced modulator 7 which also receives an input at frequency fc from carrier oscillator 8, the output of the modulator is applied via a vestigial side-band filter 9 to the transmission path. The response of the vestigial side-band filter is such that no upper sideband signals greater in frequency than fc + f1 are transmitted. The unit 5 may take several forms, e.g. in the arrangement shown in Fig. 3 a D.C. signal from source 5A is added to the data signals in summing circuit 5C and this signal produces an unbalance in the modulator which allows a small amount of carrier signal to be transmitted. In the arrangement shown in Fig. 5, signal generator 20 develops a signal which is applied via logic circuitry to a summing circuit 26 in which it is added to the data signal. The resultant signal after modulation produces two side-bands fc - f3 and fc + f3 which are sufficiently close to the carrier for the upper side-band to be passed by the vestigial sideband filter. At the receiver the signals are amplified and applied to a filter 12 which is the complement of the V.S.B. filter and hence passes signals in the range fc - f1 to fc + f1, these signals are applied to a square low detector which produces an output signal at 2fc. This signal after clipping is applied via a narrow band filter 15, delay network 16, in which its phase may be adjusted, limiter 17 and " divide by two " circuit 18 to a balanced demodulator 10 to which the input signal is also applied.