公开(公告)号：CA2051175A1

公开(公告)日：1992-04-02

申请号：CA2051175

申请日：1991-09-11

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL C ,  BLAND PATRICK M ,  STUTES RODGER M

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F13/16

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.