公开(公告)号：CA2050950A1

公开(公告)日：1992-04-02

申请号：CA2050950

申请日：1991-09-11

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL C ,  STUTES RODGER M

IPC: G06F12/06 ,  G11C8/12

Abstract: A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.

公开(公告)号：CA2051175A1

公开(公告)日：1992-04-02

申请号：CA2051175

申请日：1991-09-11

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL C ,  BLAND PATRICK M ,  STUTES RODGER M

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F13/16

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：CA2051175C

公开(公告)日：1998-03-31

申请号：CA2051175

申请日：1991-09-11

Applicant: IBM

Inventor： STUTES RODGER M ,  BLAND PATRICK M ,  CROMER DARYL C ,  ALDEREGUIA ALFREDO

IPC: G11C11/401 ,  G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G06F13/42 ,  G11C11/407 ,  G06F13/16

Abstract: A data processing system includes a memory controller for accessing a dynamic memory having a plurality of SIMMs that differ in size and speed of operation. The memory controller is operable in response to a request to access a given SIMM to read a SIMM definition register and dynamically produce memory access signals in accordance with the timing requirements of the particular SIMM being accessed. Such signals are set each time a SIMM is accessed. The signals provide different clock periods of RAS precharge time, RAS to CAS time, and CAS pulse width.

公开(公告)号：CA2050950C

公开(公告)日：1996-01-02

申请号：CA2050950

申请日：1991-09-11

Applicant: IBM

Inventor： ALDEREGUIA ALFREDO ,  CROMER DARYL C ,  STUTES RODGER M

IPC: G06F12/06 ,  G11C8/12

Abstract: A data processing system includes a processor for accessing a memory in either a direct mode or an indirect mode. The memory includes at least two memory banks and two decoders for decoding bank addresses. The decoders produce bank select signals. In direct mode, the decoder outputs are generated according to which bank is addressed. In interleave mode, the two decoder outputs are ANDed to select both banks covering the address range of the selected banks.