公开(公告)号：WO2006088533A3

公开(公告)日：2007-09-27

申请号：PCT/US2005043464

申请日：2005-12-02

Applicant: IBM ,  ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER EMANUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

Inventor： ANDRICACOS PANAYOTIS C ,  CANAPERI DONALD F ,  COOPER EMANUEL I ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  ECONOMIKOS LAERTIS ,  EDELSTEIN DANIEL C ,  FRANZ SILVIA ,  PRANATHARTHIHARAN BALASUBRAMAN ,  KRISHNAN MAHADEVAIYER ,  MANSSON ANDREW P ,  WALTON ERICK G ,  WEST ALAN C

IPC: B23H3/00

CPC classification number: C25F3/02 ,  B23H5/08 ,  C09G1/04 ,  H01L21/32125

Abstract: Methods and compositions for electro-chemical-mechanical polishing (e-CMP) of silicon chip interconnect materials, such as copper, are provided. The methods include the use of compositions according to the invention in combination with pads having various configurations.

Abstract translation: 提供了诸如铜之类的硅芯片互连材料的电化学机械抛光（e-CMP）的方法和组合物。 所述方法包括使用根据本发明的组合物与具有各种构型的垫组合。

公开(公告)号：JP2007297714A

公开(公告)日：2007-11-15

申请号：JP2007120448

申请日：2007-05-01

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BASKER VEERARAGHAVAN S ,  JOHN MICHAEL COTT ,  DELIGIANNI HARIKLIA ,  FLOTTA MATTEO

IPC: C25D7/12 ,  C25F3/12 ,  H01L21/3063 ,  H01L21/316

CPC classification number: C25D5/54 ,  C25D5/006 ,  C25D5/02 ,  C25D7/123 ,  C25D11/005 ,  C25D11/024 ,  C25D17/001 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/2885

Abstract: PROBLEM TO BE SOLVED: To provide the electrochemical processing of thin films directly on semiconducting or insulating layers and an apparatus for implementing such processes.
SOLUTION: An electrochemical process comprising steps of: providing a 125 mm or larger semiconductor wafer in electrical contact with a conducting surface, wherein at least a portion of the semiconductor wafer is in contact with an electrolytic solution, the semiconductor wafer functioning as a first electrode; providing a second electrode in the electrolytic solution, the first and second electrode connected to opposite ends of an electric power source; and irradiating a surface of the semiconductor wafer with a light source as an electric current is applied across the first and the second electrodes. The invention is also directed to an apparatus including a light source and electrochemical components to conduct the electrochemical process.
COPYRIGHT: (C)2008,JPO&INPIT

Abstract translation: 要解决的问题：提供直接在半导体或绝缘层上的薄膜的电化学处理和用于实现这些工艺的装置。 解决方案：电化学方法，包括以下步骤：提供与导电表面电接触的125mm或更大的半导体晶片，其中半导体晶片的至少一部分与电解液接触，所述半导体晶片作为 第一电极; 在所述电解液中提供第二电极，所述第一和第二电极连接到电源的相对端; 并且在第一和第二电极之间施加用作为电流的光源照射半导体晶片的表面。 本发明还涉及一种包括光源和用于进行电化学过程的电化学组分的设备。 版权所有（C）2008，JPO＆INPIT

公开(公告)号：JP2010206212A

公开(公告)日：2010-09-16

申请号：JP2010098911

申请日：2010-04-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ANDRICACOS PANAYOTIS CONSTANTINOU ,  DELIGIANNI HARIKLIA ,  DUKOVIC JOHN OWEN ,  HORKANS WILMA J ,  UZOH CYPRIAN EMEKA ,  WONG KWONG-HON ,  HU CHAO-KUN ,  EDELSTEIN DANIEL CHARLES ,  RODBELL KENNETH PARKER ,  HURD JEFFREY LOUIS

IPC: H01L21/3205 ,  C25D3/38 ,  C25D7/12 ,  H01L21/288 ,  H01L21/768 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a submicron interconnection structure for an integrated circuit. SOLUTION: A seamless conductor without void can be obtained by electroplating Cu from a bath, usually employed for adhering Cu metal which comprises an adhering agent and which is flat, glossy, ductile and low stress. The capability of this method which permits super feature fill up without leaving void or seam is unique and more excellent than any other adhering methods. The resistance of electromigration having a structure utilizing Cu electroplated by this method is superior to the resistance of electromigration having a structure manufactured by employing Cu adhered in an AlCu structure or by a method except electroplating. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：提供一种用于集成电路的亚微米互连结构的制造方法。 解决方案：通过从浴中电镀Cu，通常用于粘附包含粘合剂的Cu金属并且是平坦的，有光泽的，延性的和低应力的，可以获得无空隙的无缝导体。 这种允许超级特征填充而不留下空隙或接缝的方法的能力是独特的，比任何其他粘合方法更优异。 具有利用通过该方法电镀的Cu的结构的电迁移电阻优于具有通过使用以AlCu结构附着的Cu制造的结构的电迁移的电阻或通过除电镀之外的方法。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2004162177A

公开(公告)日：2004-06-10

申请号：JP2003348876

申请日：2003-10-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ECONOMIKOS LAERTIS ,  DELIGIANNI HARIKLIA ,  COTTE JOHN M ,  ANDRICACOS PANAYOTIS C

IPC: C25D5/04 ,  C25D5/48 ,  C25D7/12 ,  C25D17/00 ,  C25D21/00 ,  C25F3/12 ,  C25F7/00 ,  H01L21/288

CPC classification number: C25D5/48 ,  C25D17/00 ,  C25D17/001 ,  C25D17/10

Abstract: PROBLEM TO BE SOLVED: To provide an integrated plating and planarization apparatus having a counter electrode with a variable diameter.
SOLUTION: The apparatus for plating and planarizing a metal on a substrate is provided with a plurality of distribution segments each of which has at least one hole for distributing an electroplating solution onto the substrate. The distribution segments form a circular counter electrode and is movable with respect to each other during an electroplating process so that the counter electrode may have a variable diameter. Thus, the electroplating solution is distributed onto the annular part of the substrate having a diameter corresponding to the diameter of the counter electrode. Therefore, the counter electrode can allow the local delivery of the plating solution onto the substrate.
COPYRIGHT: (C)2004,JPO

公开(公告)号：JP2009065207A

公开(公告)日：2009-03-26

申请号：JP2008314245

申请日：2008-12-10

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  DELIGIANNI HARIKLIA ,  DUKOVIC JOHN OWEN ,  HORKANS WILMA J ,  UZOH CYPRIAN EMEKA ,  WONG KWONG-HON ,  HU CHAO-KUN ,  EDELSTEIN DANIEL CHARLES ,  RODBELL KENNETH PARKER ,  HURD JEFFREY LOUIS

IPC: H01L21/288 ,  C25D3/38 ,  C25D7/12 ,  H01L21/28 ,  H01L21/3205 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing submicron interconnection structures for integrated circuits.
SOLUTION: A void-less and seamless conductor can be obtained by electro-plating copper (Cu) in an ordinary additive-containing bath used to plate flat, glossy, ductile, and low stress copper metal. This method capable of super-filling features without leaving voids or seams has a unique capability and is superior to any other methods. The electromigration resistance of a structure utilizing Cu electroplated by this method is superior to the electromigration resistance of an AlCu structure or a structure manufactured using copper deposited by any other method than electroplating.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：提供一种制造用于集成电路的亚微米互连结构的方法。

解决方案：通过在用于平板，光泽，延性和低应力铜金属的普通添加剂浴中电镀铜（Cu），可以获得无孔隙和无缝导体。 这种能够超级填充特征而不留下空隙或接缝的方法具有独特的能力并且优于任何其它方法。 利用这种方法电镀Cu的结构的电迁移电阻优于AlCu结构的电迁移电阻或使用除电镀之外的任何其它方法沉积的铜制成的结构。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2007194624A

公开(公告)日：2007-08-02

申请号：JP2006353015

申请日：2006-12-27

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： MALHOTRA SANDRA G ,  DELIGIANNI HARIKLIA ,  VAN DER STRATEN OSCAR ,  SHAO XIAOYAN ,  ROSSNAGEL STEPHEN M ,  TAI TSONG-LIN

IPC: H01L23/52 ,  C23C16/16 ,  C23C16/56 ,  C25D7/12 ,  H01L21/288 ,  H01L21/3205

CPC classification number: H01L21/76843 ,  H01L21/28562 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  Y10S438/952

Abstract: PROBLEM TO BE SOLVED: To provide a process for direct electroplating of copper on a platable layer which is not copper.
SOLUTION: This process for forming an interconnection in a semiconductor structure comprises a step for forming a dielectric layer on a substrate, a step for forming a first barrier layer on the dielectric layer, and a step for forming a second barrier layer on the first barrier layer. The second barrier layer is selected from a group including ruthenium, platinum, palladium, rhodium and iridium. The second barrier layer is formed by a process including a step for manipulating so that bulk concentration of oxygen in the second barrier layer becomes 20 atm.% or less, and a step for forming a conductive layer on the second barrier layer. This process further can include a step for treating the second barrier to decrease the amount of an oxide on the surface of the second barrier layer.
COPYRIGHT: (C)2007,JPO&INPIT

Abstract translation: 要解决的问题：提供在不是铜的可镀层上直接电镀铜的方法。 解决方案：用于在半导体结构中形成互连的该工艺包括在衬底上形成电介质层的步骤，在电介质层上形成第一阻挡层的步骤和用于形成第二阻挡层的步骤 第一阻隔层。 第二阻挡层选自包括钌，铂，钯，铑和铱的组。 第二阻挡层通过包括操作步骤的方法形成，使得第二阻挡层中的氧的体积浓度变为20atm％以下，以及在第二阻挡层上形成导电层的步骤。 该方法还可以包括用于处理第二阻挡层以减少第二阻挡层的表面上的氧化物的量的步骤。 版权所有（C）2007，JPO＆INPIT

公开(公告)号：JP2005217419A

公开(公告)日：2005-08-11

申请号：JP2005021309

申请日：2005-01-28

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： EDELSTEIN DANIEL C ,  ANDRICACOS PANAYOTIS C ,  COTTE JOHN M ,  DELIGIANNI HARIKLIA ,  MAGERLEIN JOHN H ,  PETRARCA KEVIN S ,  STEIN KENNETH JAY ,  VOLANT RICHARD P

IPC: H01F41/04 ,  H01F17/00 ,  H01L21/02 ,  H01L23/485 ,  H01L23/522 ,  H01L23/532 ,  H01L27/08

CPC classification number: H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To provide an inductor and a method of forming the inductor. SOLUTION: The method of forming the inductor comprises (a) a step for providing a semiconductor substrate, (b) a step for forming a dielectric layer on the surface of the substrate, (c) a step for forming a lower trench in the dielectric layer, (d) a step for forming a resist layer on the surface of the dielectric layer, (e) a step for forming an upper trench which is aligned to the lower trench and whose bottom is opened for the lower trench in the resist layer, and (f) a step for completely filling the lower trench with a conductor and at least partially filling the upper trench with the conductor to form the inductor. The semiconductor structure includes the inductor including the upper surface, bottom surface and sidewall and a means that allows the inductor to be electrically contacted, the lower section of the inductor is extended by a distance that the lower section of the inductor is fixed in the dielectric layer formed on the substrate, and the upper section thereof is extended on the dielectric layer. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供电感器和形成电感器的方法。 形成电感器的方法包括（a）提供半导体衬底的步骤，（b）在衬底的表面上形成电介质层的步骤，（c）形成下沟槽的步骤 在电介质层中，（d）在电介质层的表面上形成抗蚀剂层的步骤，（e）形成上沟槽的步骤，该上沟槽与下沟槽对准并且底部为下沟槽开口 抗蚀剂层，和（f）用导体完全填充下沟槽并且至少部分地用导体填充上沟槽以形成电感器的步骤。 半导体结构包括电感器，其包括上表面，底表面和侧壁，以及允许电感器电接触的装置，电感器的下部延伸一段距离，电感器的下部固定在电介质中 层，其上部在电介质层上延伸。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2005136433A

公开(公告)日：2005-05-26

申请号：JP2004362864

申请日：2004-12-15

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： ANDRICACOS PANAYOTIS CONSTANTI ,  DELIGIANNI HARIKLIA ,  DUKOVIC JOHN OWEN ,  HORKANS WILMA J ,  UZOH CYPRIAN EMEKA ,  WONG KWONG-HON ,  HU CHAO-KUN ,  EDELSTEIN DANIEL CHARLES ,  RODBELL KENNETH PARKER ,  HURD JEFFREY LOUIS

IPC: C25D3/38 ,  C25D7/12 ,  H01L21/288 ,  H01L21/3205 ,  H01L23/52

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a submicron interconnection structure for an integrated circuit.
SOLUTION: By electroplating Cu in a bath which includes an additive and is usually used for adhering Cu metal which is flat and glossy and has high ductility and low stress, seamless semiconductor without void is obtained. This method allows a feature to be super-filled up without leaving void or seam. The resistance of electromigration with the structure utilizing Cu which is electroplated by this method is more excellent than the resistance of electromigration with the structure manufactured using Cu which is adhered by methods other than AlCu structure or electroplating.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种用于集成电路的亚微米互连结构的制造方法。 解决方案：通过在包含添加剂的浴中电镀Cu，通常用于粘附平坦且光滑且具有高延展性和低应力的Cu金属，获得无空隙的无缝半导体。 这种方法允许特征被超填充而不留下空隙或接缝。 利用该方法电镀Cu结构的电迁移电阻比使用除AlCu结构或电镀以外的方法附着的Cu制造的结构的电迁移电阻更好。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2003249137A

公开(公告)日：2003-09-05

申请号：JP2002330991

申请日：2002-11-14

Applicant: IBM

Inventor： GREENBERG DAVID R ,  DELIGIANNI HARIKLIA ,  ROBERT A GROVES ,  CHRISTOPHER V JARNES ,  LUND JENNIFER L ,  CATHERINE L SAENGER ,  VOLANT RICHARD P

IPC: B81B3/00 ,  H01H1/24 ,  H01H1/26 ,  H01H59/00

Abstract: PROBLEM TO BE SOLVED: To provide a fine electric mechanical switch having a restoring force large enough to overcome static friction. SOLUTION: This fine electric mechanical switch comprises a conductive beam 10 capable of being warped, and a plurality of electrodes which are covered with elastically deformable conductive layers 11. At first, a restoring force is generated by a single spring constant k0 of the beam 10 by applying a control voltage between the beam 10 capable of being warped and a control electrode 12 which is flush with a switch electrode 13. Then, when the fine electric mechanical switch is approached to the closed state and the conductive layers 11 are compressed, restoring forces due to additional spring constants, k1,..., kn of the plurality of deformable conductive layers 11 are sequentially added to the restoring force due to the spring constant k0 of the beam 10. In another embodiment, deformable spring-like elements are used in place of the deformable layers. Furthermore in the other embodiment, compressible layers or the deformable spring-like elements are mounted on the warping beam which is opposed to the switch electrode. COPYRIGHT: (C)2003,JPO

公开(公告)号：WO2007112361A3

公开(公告)日：2008-04-10

申请号：PCT/US2007064946

申请日：2007-03-26

Applicant: IBM ,  CABRAL CYRIL JR ,  DELIGIANNI HARIKLIA ,  KNARR RANDOLPH F ,  MALHOTRA SANDRA G ,  ROSSNAGEL STEPHEN ,  SHAO XIAOYAN ,  TOPOL ANNA ,  VEREECKEN PHILIPPE M

Inventor： CABRAL CYRIL JR ,  DELIGIANNI HARIKLIA ,  KNARR RANDOLPH F ,  MALHOTRA SANDRA G ,  ROSSNAGEL STEPHEN ,  SHAO XIAOYAN ,  TOPOL ANNA ,  VEREECKEN PHILIPPE M

IPC: H01L29/02

CPC classification number: H01L23/485 ,  H01L21/2885 ,  H01L21/76843 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/53252 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a suicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the suicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.

Abstract translation: 一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的自杀或锗化物层，例如钴和/或镍; 接触层包括位于介电层顶部并且在空腔内并且与底部上的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。 金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。 当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。 当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。