公开(公告)号：PL364643A1

公开(公告)日：2004-12-13

申请号：PL36464301

申请日：2001-12-21

Applicant: IBM

Inventor： BILARDI GIANFRANCO ,  PATTNAIK PRATAP CHANDRA ,  EKANADHAM KATTAMURI

IPC: G06F9/30 ,  G06F9/312 ,  G06F9/34 ,  G06F9/38

Abstract: A method and apparatus for issuing and executing memory instructions from a computer system so as to (1) maximize the number of requests issued to a highly pipe-lined memory, the only limitation being data dependencies in the program and (2) avoid reading data from memory before a corresponding write to memory. The memory instructions are organized to read and write into memory, by using explicit move instructions, thereby avoiding any data storage limitations in the processor. The memory requests are organized to carry complete information, so that they can be processed independently when memory returns the requested data. The memory is divided into a number of regions, each of which is associated with a fence counter. The fence counter for a memory region is incremented each time a memory instruction that is targeted to the memory region is issued and decremented each time there is a write to the memory region. After a fence instruction is issued, no further memory instructions are issued if the counter for the memory region specified in the fence instruction is above a threshold. When a sufficient number of the outstanding issued instructions are executed, the counter will be decremented below the threshold and further memory instructions are then issued.

公开(公告)号：GB2318660B

公开(公告)日：2001-07-04

申请号：GB9719580

申请日：1997-09-16

Applicant: IBM

Inventor： RECHTSCHAFFEN RUDOLPH NATHAN ,  EKANADHAM KATTAMURI

IPC: G06F9/38 ,  G06F9/45 ,  G06F15/80 ,  G06F9/44

Abstract: An apparatus and method for self-parallelizing and executing a sequence of instructions. During a first mode of operation, instructions are executed concurrently with the parallelizing of instructions sequences not already parallelized. During a second mode of operation, instruction sequences already parallelized during the first mode are executed in parallel asynchronously by separate processors. The separate processors share a common register file. The processing elements rename the registers used by the instructions that modify registers so when instructions are executed in parallel the result of the executions appear in the common set of registers accessible to all the processing elements. There is no need to send and receive obligation to resolve register set/use requirements implied by the sequential execution sequence.