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    Artificial neuron apparatus
    12.
    发明专利
    Artificial neuron apparatus 未知

    公开(公告)号：GB2565243A

    公开(公告)日：2019-02-06

    申请号：GB201816545

    申请日：2017-02-24

    Applicant: IBM

    Inventor： EVANGELOS STAVROS ELEFTHERIOU ,  LUKAS KULL ,  ANGELIKI PANTAZI ,  ABU SEBASTIAN ,  TOMAS TUMA ,  MILOS STANISAVLJEVIC

    IPC: G06N3/063

    Abstract: Artificial neuron apparatus includes a resistive memory cell connected in an input circuit having a neuron input, for receiving neuron input signals, and a current source for supplying a read current to the cell. The input circuit is selectively configurable in response to a set of control signals, defining alternating read and write phases of operation, to apply the read current to the cell during the read phase and to apply a programming current to the cell, for programming cell resistance, on receipt of a neuron input signal during the write phase. The cell resistance is progressively changed from a first state to a second state in response to successive neuron input signals. The apparatus further includes an output circuit comprising a neuron output and a digital latch which is connected to the input circuit for receiving a measurement signal dependent on cell resistance.

    Training of artificial neural networks
    15.
    发明专利
    Training of artificial neural networks 未知

    公开(公告)号：GB2581731B

    公开(公告)日：2022-11-09

    申请号：GB202006982

    申请日：2018-10-23

    Applicant: IBM

    Inventor： MANUEL LE GALLO-BOURDEAU ,  ABU SEBASTIAN ,  IREM BOYBAT KARA ,  EVANGELOS STAVROS ELEFTHERIOU ,  NANDAKUMAR SASIDHARAN RAJALEKSHMI

    IPC: G06N3/08 ,  G06N3/063

    Abstract: Methods and apparatus are provided for training an artificial neural network having a succession of layers of neurons interposed with layers of synapses. A set of crossbar arrays of memristive devices, connected between row and column lines, implements the layers of synapses. Each memristive device stores a weight for a synapse interconnecting a respective pair of neurons in successive neuron layers. The training method includes performing forward propagation, backpropagation and weight-update operations of an iterative training scheme by applying input signals, associated with respective neurons, to row or column lines of the set of arrays to obtain output signals on the other of the row or column lines, and storing digital signal values corresponding to the input and output signals. The weight-update operation is performed by calculating digital weight-correction values for respective memristive devices, and applying programming signals to those devices to update the stored weights.

    Training of artificial neural networks
    16.
    发明专利
    Training of artificial neural networks 未知

    公开(公告)号：GB2581731A

    公开(公告)日：2020-08-26

    申请号：GB202006982

    申请日：2018-10-23

    Applicant: IBM

    Inventor： MANUEL LE GALLO-BOURDEAU ,  ABU SEBASTIAN ,  IREM BOYBAT KARA ,  EVANGELOS STAVROS ELEFTHERIOU ,  NANDAKUMAR SASIDHARAN RAJALEKSHMI

    IPC: G06N3/08 ,  G06N3/063

    Abstract: Methods and apparatus are provided for training an artificial neural network having a succession of layers of neurons interposed with layers of synapses. A set of crossbar arrays of memristive devices, connected between row and column lines, implements the layers of synapses. Each memristive device stores a weight Ŵ for a synapse interconnecting a respective pair of neurons in successive neuron layers. The training method comprises performing forward propagation, backpropagation and weight-update operations of an iterative training scheme by, in at least one of the forward propagation and backpropagation operations of the scheme, applying input signals, associated with respective neurons, to one of row and column lines of the set of arrays to obtain output signals on the other of the row and column lines, and storing digital signal values corresponding to the input and output signals in a digital processing unit operatively coupled to the set of arrays. The weight-update operation of the scheme is performed by calculating, in the digital processing unit, digital weight-correction values ΔW, dependent on the stored digital signal values, for respective memristive devices, and applying programming signals to those devices to update the stored weights Ŵ in dependence on the respective digital weight-correction values ΔW.

    Neuromorphic processing devices
    17.
    发明专利
    Neuromorphic processing devices 未知

    公开(公告)号：GB2556550A

    公开(公告)日：2018-05-30

    申请号：GB201801088

    申请日：2016-06-08

    Applicant: IBM

    Inventor： EVANGELOS STAVROS ELEFTHERIOU ,  MANUEL LE GALLO ,  ANGELIKI PANTAZI ,  ABU SEBASTIAN ,  TOMAS TUMA

    IPC: G06N3/04 ,  G06N3/063

    Abstract: A neuromorphic processing device (1) has a device input (2), for receiving an input data signal, and an assemblage of neuron circuits (3). Each neuron circuit (3) comprises a resistive memory cell (14) which is arranged to store a neuron state, indicated by cell resistance, and to receive neuron input signals (11) for programming cell resistance to vary the neuron state, and a neuron output circuit (15) for supplying a neuron output signals (12) in response to cell resistance traversing a threshold. The device (1) includes an input signal generator (4) connected to the device input (2) and the assemblage of neuron circuits (3), for generating neuron input signals (11) for the assemblage in dependence on the input data signal. The device (1) further includes a device output circuit (5), connected to neuron output circuits (15) of the assemblage, for producing a device output signal dependent on neuron output signals (12) of the assemblage, whereby the processing device (1) exploits stochasticity of resistive memory cells of the assemblage.

    Neuromorphic synapses
    18.
    发明专利
    Neuromorphic synapses 未知

    公开(公告)号：GB2552577B

    公开(公告)日：2018-05-02

    申请号：GB201708045

    申请日：2015-10-13

    Applicant: IBM

    Inventor： EVANGELOS STAVROS ELEFTHERIOU ,  ANGELIKI PANTAZI ,  ABU SEBASTIAN ,  TOMAS TUMA

    IPC: G06N3/063

    Abstract: A neuromorphic synapse with a resistive memory cell connected in circuitry having first and second input terminals. The input terminals respectively receive pre-neuron and post-neuron action signals, each having a read portion and a write portion, in use. The circuitry includes an output terminal for providing a synaptic output signal which is dependent on resistance of the memory cell. The circuitry is configured such that the synaptic output signal is provided at the output terminal in response to application at the first input terminal of the read portion of the pre-neuron action signal, and such that a programming signal, for programming resistance of the memory cell, is applied to the cell in response to simultaneous application of the write portions of the pre-neuron and post-neuron action signals at the first and second input terminals respectively. The synapse can be adapted for operation with identical pre-neuron and post-neuron action signals.

    Method and apparatus for operating a storage device
    20.
    发明专利
    Method and apparatus for operating a storage device 未知

    公开(公告)号：GB2490828B

    公开(公告)日：2017-05-10

    申请号：GB201214600

    申请日：2011-01-27

    Applicant: IBM

    Inventor： EVANGELOS STAVROS ELEFTHERIOU ,  WALTER HAEBERLE ,  JENS JELITTO ,  ANGELIKI PANTAZI

    IPC: G11B5/584

    Abstract: Method for operating a storage device with a tape and a head wherein the head comprises a first and a second read element. Each read element is operable to detect servo-pattern of a particular servo band. The first and the second read element are arranged such that the tape at first passes one of both read elements and subsequently passes the other of both read elements when the tape moves in a predetermined longitudinal direction. A tape transport direction of the tape along the longitudinal direction is determined. The first read element is selected dependent on the determined tape transport direction, when the determined tape transport direction represents a direction where the tape at first passes the first read element and subsequently the second read element. Otherwise the second read element is selected. A position error signal is determined dependent on the selected read element.

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