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公开(公告)号:GB2532055A
公开(公告)日:2016-05-11
申请号:GB201419824
申请日:2014-11-07
Applicant: IBM
Inventor: FABRICE JEAN VERPLANKEN , FRANCOIS ABEL , CLAUDE BASSO , PHILIPPE DAMON
Abstract: A packet parser 9 has a set of marker elements (21, Figure 3) each comprising a one bit latch and connected to store flag values from the results of the application of parser rules. Some marker elements are connected to provide the stored marker values as input to the parser rule logic to be taken into account in the processing of subsequent parser rules and some are connected to control external hardware. Some markers are reset at the end of each packet. A special toggle marker element toggles its value when its address is selected and other marker elements are connected to store, when its own address is selected, the value of the toggle element. Other markers toggle their own value when selected. The packet parser comprises a rule processor 10 which applies parsing rules to data from a data packet and supplies a result address value. The rule processor extracts the marker element address value from a field of a processor rule. The new value stored in the selected marker may be based on a value of one of the marker elements of the plurality of marker elements, such as the previous value of the selected marker, based on being different to the default value of the selected marker element or based on the value of a special marker element. The special marker element may invert its value when enabled and supplies its stored value, or a value based thereon, as the input of the selected marker element.
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公开(公告)号:SG111013A1
公开(公告)日:2005-05-30
申请号:SG200007701
申请日:2000-12-28
Applicant: IBM
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公开(公告)号:GB2532054B
公开(公告)日:2016-10-12
申请号:GB201419819
申请日:2014-11-07
Applicant: IBM
Inventor: FABRICE JEAN VERPLANKEN , JEAN-PAUL ALDEBERT , JEAN-LUC FRENOY , CLAUDE BASSO
IPC: G06F13/38 , G06F13/362
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公开(公告)号:GB2532054A
公开(公告)日:2016-05-11
申请号:GB201419819
申请日:2014-11-07
Applicant: IBM
Inventor: FABRICE JEAN VERPLANKEN , JEAN-PAUL ALDEBERT , JEAN-LUC FRENOY , CLAUDE BASSO
Abstract: A Network Controller-Sideband Interface (NC-SI) Port Controller (NPC) 23 of a Network Interface Controller (NIC) provides a sideband connection between the network 2 and a Baseboard Management Controller (BMC) 17. Pass-through traffic to and from the BMC are injected and extracted by the XBB 16 and RBB 6 units of the Host Ethernet Adapter 3 part of the NIC. Asynchronous event notification (AEN) pseudopackets giving status information about the NIC are compiled 28 and injected into the data route of the NPC that carries packets from the BMC. Both of those kinds of packet pass by a packet parser 30 with the AEN pseudo-packets being dropped but their content being assembled by the NPC into an AEN packet which is then injected into the data route of the NPC that carries packets bound for the BMC. The packet parser analyses data transmitted from the sideband endpoint (BMC) towards the network and identifies NC-SI requests from the BMC and provides response packets in the same way. The NIC also comprises a Media Access Controller 4. The HEA comprises a host buffer to store a packet from the host; a sideband buffer to store a packet from the NPC and an arbiter connected to allow, at different times, a packet in the host buffer and a packet in the sideband buffer, to advance from there along a transmit route to the MAC. In-Band packets may have higher priority than sideband packets.
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公开(公告)号:GB2532053A
公开(公告)日:2016-05-11
申请号:GB201419818
申请日:2014-11-07
Applicant: IBM
Inventor: FABRICE JEAN VERPLANKEN , JEAN-PAUL ALDEBERT , JEAN-LUC FRENOY , CLAUDE BASSO
IPC: G06F13/38 , H04L47/32 , H04L47/2466 , H04L47/80
Abstract: A Network Controller-Sideband Interface (NC-SI) Port Controller (NPC) 23 of a Network Interface Controller (NIC) provides a sideband connection between the network 2 and a Baseboard Management Controller (BMC) 17. Pass-through traffic to and from the BMC are injected and extracted by the XBB 16 and RBB 6 units of the Host Ethernet Adapter 3 part of the NIC. Asynchronous event notification (AEN) pseudopackets giving status information about the NIC are compiled 28 and injected into the data route of the NPC that carries packets from the BMC. Both of those kinds of packet pass by a packet parser 30 with the AEN pseudo-packets being dropped but their content being assembled by the NPC into an AEN packet which is then injected into the data route of the NPC that carries packets bound for the BMC. The packet parser analyses data transmitted from the sideband endpoint (BMC) towards the network and identifies NC-SI requests from the BMC and provides response packets in the same way. A buffer may be employed in the transmit route for packets from the BMC headed towards the network. The buffer may employ a sliding window circuit connect ro provide a section of the data in the buffer to the packet parser. The NPC may also comprise an arbiter 21, 22, to arbitrate traffic to or from the BMC.
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公开(公告)号:HK1052263B
公开(公告)日:2006-02-03
申请号:HK03104440
申请日:2003-06-20
Applicant: IBM
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公开(公告)号:SG90222A1
公开(公告)日:2002-07-23
申请号:SG200007697
申请日:2000-12-28
Applicant: IBM
Inventor: BRIAN MITCHELL BASS , JEAN LOUIS CALVIGNAC , MARCO C HEDDES , STEVEN KENNETH JENKINS , MICHAEL STEVEN SIEGEL , MICHAEL RAYMOND TROMBLEY , FABRICE JEAN VERPLANKEN
IPC: G06F12/06 , G06F12/00 , G06F12/02 , G06F13/00 , G06F13/16 , G06F15/167 , G11C11/407 , H04L12/56
Abstract: The ability of network processors to move data to and from dynamic random access memory (DRAM) chips used in computer systems is enhanced in several respects. In one aspect of the invention, two double data rate DRAMS are used in parallel to double the bandwidth for increased throughput of data. The movement of data is further improved by setting 4 banks of full "read' and 4 banks of full "write' by the network processor for every repetition of the DRAM time clock. A scheme for randomized "read' and "write' access by the network processor is disclosed. This scheme is particularly applicable to networks such as Ethernet that utilize variable frame sizes.
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