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公开(公告)号：HU0203928A2
公开(公告)日：2003-04-28
申请号：HU0203928
申请日：2000-11-21
Inventor： AYDEMIR METIN , BASS BRIAN MITCHELL , GALLO ANTHONY MATTEO , GORTI BRAHMANAND KUMAR , HEDDES MARCO , JEFFRIES CLARK DEBS , ROVNER SONIA KIANG , SIEGEL MICHAEL STEVEN
Abstract: Methods, apparatus and program products for controlling a flow of a plurality of packets in a computer network are disclosed. The computer network includes a device defining a queue. The methods, apparatus and program products include determining a queue level for the queue and determining an offered rate of the plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, based on the queue level, the offered rate and a previous value of the transmission fraction so that the transmission fraction and the queue level are critically damped if the queue level is between at least a first queue level and a second queue level. Several embodiments are disclosed in which various techniques are used to determine the manner of the control.
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公开(公告)号：DE60042493D1
公开(公告)日：2009-08-13
申请号：DE60042493
申请日：2000-11-21
Applicant: IBM
Inventor： AYDEMIR METIN , BASS BRIAN MITCHELL , JEFFRIES CLARK DEBS , ROVNER SONIA KIANG , SIEGEL MICHAEL STEVEN , GALLO ANTHONY MATTEO , GORTI BRAHMANAND KUMAR , HEDDES MARCO
IPC: H04L47/30
Abstract: Methods, apparatus and program products for controlling a flow of a plurality of packets in a computer network are disclosed. The computer network includes a device defining a queue. The methods, apparatus and program products include determining a queue level for the queue and determining an offered rate of the plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, based on the queue level, the offered rate and a previous value of the transmission fraction so that the transmission fraction and the queue level are critically damped if the queue level is between at least a first queue level and a second queue level. Several embodiments are disclosed in which various techniques are used to determine the manner of the control.
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公开(公告)号：CA2387101C
公开(公告)日：2006-01-03
申请号：CA2387101
申请日：2000-11-21
Applicant: IBM
Inventor： GALLO ANTHONY MATTEO , ROVNER SONIA KIANG , SIEGEL MICHAEL STEVEN , JEFFRIES CLARK DEBS , HEDDES MARCO , GORTI BRAHMANAND KUMAR , BASS BRIAN MITCHELL , AYDEMIR METIN
IPC: H04L47/30
Abstract: Methods, apparatus and program products for controlling a flow of a pluralit y of packets in a computer network are disclosed. The computer network include s a device defining a queue. The methods, apparatus and program products inclu de determining a queue level for the queue and determining an offered rate of t he plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, base d on the queue level, the offered rate and a previous value of the transmissio n fraction so that the transmission fraction and the queue level are criticall y damped if the queue level is between at least a first queue level and a seco nd queue level. Several embodiments are disclosed in which various techniques a re used to determine the manner of the control.
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公开(公告)号：AT280411T
公开(公告)日：2004-11-15
申请号：AT00983409
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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公开(公告)号：AU2016601A
公开(公告)日：2001-07-16
申请号：AU2016601
申请日：2000-12-21
Applicant: IBM
Inventor： CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH , LEAVENS ROSS BOYD , SIEGEL MICHAEL STEVEN , VERPLANKEN FABRICE JEAN
Abstract: A system and method of frame protocol classification and processing in a system for data processing (e.g., switching or routing data packets or frames). The present invention includes analyzing a portion of the frame according to predetermined tests, then storing key characteristics of the packet for use in subsequent processing of the frame. The key characteristics for the frame (or input information unit) include the type of layer 3 protocol used in the frame, the layer 2 encapsulation technique, the starting instruction address, flags indicating whether the frame uses a virtual local area network, and the identity of the data flow to which the frame belongs. Much of the analysis is preferably done using hardware so that it can be completed quickly and in a uniform time period. The stored characteristics of the frame are then used by the network processing complex in its processing of the frame. The processor is preconditioned with a starting instruction address and the location of the beginning of the layer 3 header as well as flags for the type of frame. That is, the instruction address or code entry point is used by the processor to start processing for a frame at the right place, based on the type of frame. Additional instruction addresses can be stacked and used sequentially at branches to avoid additional tests and branching instructions. Additionally, frames comprising a data flow can be processed and forwarded in the same order in which they are received.
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Patent Agency Ranking
公开(公告)号：DE60117063D1
公开(公告)日：2006-04-20
申请号：DE60117063
申请日：2001-03-16
Applicant: IBM
Inventor： BASSO CLAUDE , DAMON PHILIPPE , GALLO ANTHONY MATTEO
Abstract: A system for providing a scalable processor and operating system independent network processor services architecture. The system includes a plurality of portable and individualised functional components representing particular segments of the control processor's device driver. The functional components, which include lower level and external APIs, carry out the various network processor functions such as the receipt and transfer of packets on the network, and other functions required by the control processor to communicate with and direct the network processor. The functional components are designed to be adaptable to the various types of processor architecture and operating systems available and to permit customers or developers to customise and expand the available network services.
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公开(公告)号：ES2226958T3
公开(公告)日：2005-04-01
申请号：ES00983409
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH
Abstract: Un aparato que comprende: un substrato semiconductor; N unidades (110) de procesamiento fabricadas sobre el substrato, donde N > 1; una primera memoria de datos interna accesible para dichas N unidades de procesamiento; una unidad (112) de expedición acoplada operativamente a las N unidades de procesamiento para recibir y transmitir una unidad de información de entrada a una de las N unidades de procesamiento; una unidad (118) de clasificación acoplada a la unidad (112) de expedición, incluyendo dicha unidad de clasificación una unidad (114) de comparación para determinar un formato de datos para una unidad de información de entrada y para generar y almacenar en la memoria de datos interna indicadores de salida para la unidad de información de entrada, que indican el formato de datos de la unidad de información de entrada y una dirección de arranque para la unidad de información de entrada, cuyos indicadores y dirección de arranque están disponibles para una de las N unidades de procesamiento durante su procesamiento de la unidad de información de entrada y son utilizados en el procesamiento de la unidad de información de entrada; y una unidad (114) de compleción soportada en el substrato semiconductor y conectada operativamente a las N unidades (110) de procesamiento para recibir la unidad de información procesada por la unidad considerada de las N unidades (110) de procesamiento.
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公开(公告)号：CA2387101A1
公开(公告)日：2001-05-31
申请号：CA2387101
申请日：2000-11-21
Applicant: IBM
Inventor： AYDEMIR METIN , GORTI BRAHMANAND KUMAR , HEDDES MARCO , BASS BRIAN MITCHELL , JEFFRIES CLARK DEBS , ROVNER SONIA KIANG , GALLO ANTHONY MATTEO , SIEGEL MICHAEL STEVEN
Abstract: Methods, apparatus and program products for controlling a flow of a pluralit y of packets in a computer network are disclosed. The computer network include s a device defining a queue. The methods, apparatus and program products inclu de determining a queue level for the queue and determining an offered rate of t he plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, base d on the queue level, the offered rate and a previous value of the transmissio n fraction so that the transmission fraction and the queue level are criticall y damped if the queue level is between at least a first queue level and a seco nd queue level. Several embodiments are disclosed in which various techniques a re used to determine the manner of the control.
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公开(公告)号：AT333678T
公开(公告)日：2006-08-15
申请号：AT00959158
申请日：2000-08-24
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , GALLO ANTHONY MATTEO , HEDDES MARCO C , PROPERTY LAW HURSLEY PARK , RAO SRIDHAR , SIEGEL MICHAEL STEVEN , YOUNGMAN BRIAN ALAN , VERPLANKEN FABRICE JEAN
IPC: G06F15/16 , G06F13/40 , G06F15/177 , H04L12/56 , G06F13/00 , G06F13/38 , G06F15/00 , G06F15/76 , G06F15/173
Abstract: An apparatus is disclosed for transporting control information in a communications system. The apparatus comprises a network processor, a control point processor operatively coupled to the network processor, and a guided frame generated by the control point processor. The guided frame comprises a first section in which frame control information is placed and is used by the network processor to update at least one control register within the network processor; a second section carrying correlators assigned by the control point processor to correlate guided frame responses with their requests; a third section carrying one or a sequence of guided commands; and an End delimiter guided command.
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公开(公告)号：AT317619T
公开(公告)日：2006-02-15
申请号：AT01000057
申请日：2001-03-16
Applicant: IBM
Inventor： BASSO CLAUDE , DAMON PHILIPPE , GALLO ANTHONY MATTEO
Abstract: A system for providing a scalable processor and operating system independent network processor services architecture. The system includes a plurality of portable and individualised functional components representing particular segments of the control processor's device driver. The functional components, which include lower level and external APIs, carry out the various network processor functions such as the receipt and transfer of packets on the network, and other functions required by the control processor to communicate with and direct the network processor. The functional components are designed to be adaptable to the various types of processor architecture and operating systems available and to permit customers or developers to customise and expand the available network services.
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