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公开(公告)号：SG90594G
公开(公告)日：1994-10-14
申请号：SG90594
申请日：1994-07-09
Applicant: IBM
Inventor： GAUDENZI GENE JOSEPH
IPC: H03K19/082 , H03K19/086
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公开(公告)号：DE68910964T2
公开(公告)日：1994-05-19
申请号：DE68910964
申请日：1989-04-11
Applicant: IBM
Inventor： GAUDENZI GENE JOSEPH
IPC: H03K17/04 , H03K19/013 , H03K19/082 , H03K19/086
Abstract: A circuit includes a set of seven NPN transistors (T1-T7), a Schottky diode (SD), and several resistors. The signal is connected from the input section to the output section directly from the base of a transistor (T2) in the input circuit to the base of the lower output transistor (T3), which (T2) is connected with its collector emitter connections in parallel with the emitter resistor (R3) of the input transistors which receive the input signals to the circuit. Two transistors (T1,T6) are connected to input terminals to provide a possible NOR arrangement although one of them alone can be used if the requirement of the circuit is simply for an inverter circuit. The output transistors comprise a push-pull output section (T3,T4).
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公开(公告)号：DE3676563D1
公开(公告)日：1991-02-07
申请号：DE3676563
申请日：1986-05-28
Applicant: IBM
Inventor： FAVATA ALFRED FILADELFIO , GAUDENZI GENE JOSEPH
IPC: H03K3/286 , H03K5/00 , H03K19/003 , H03K19/0175 , H03K19/082
Abstract: A digital circuit with a logical input stage (4) and an output stage (7, 8) comprises an intermediate stage (5) which operates to temporarily increase the current through the input stage (4) upon a transition from one logical level to the other. The intermediate stage (5) includes a current source (40) which is controlled by the output potential of the input stage (4) via a feedback arrangement (43) from a circuit (50) in the intermediate stage (5) controlling the output stage (7, 8).
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公开(公告)号：DE68923818T2
公开(公告)日：1996-04-18
申请号：DE68923818
申请日：1989-04-11
Applicant: IBM
Inventor： BLAND PATRICK MAURICE , KRAMER KEVIN GERRARD , DEAN MARK EDWARD , TEMPEST SUSAN LYNN , GAUDENZI GENE JOSEPH
IPC: G06F11/10 , G06F13/38 , G06F13/40 , H03K3/288 , H03K19/082 , H03K19/00 , H03K19/0175
Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes : a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data patch comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanism for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.
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Patent Agency Ranking
公开(公告)号：DE3879089D1
公开(公告)日：1993-04-15
申请号：DE3879089
申请日：1988-08-16
Applicant: IBM
Inventor： GAUDENZI GENE JOSEPH , TEMPEST SUSAN LYNN
Abstract: A voltage regulator for regulating the voltage at a first node, comprising a first voltage supply; a first node; a first transistor with a control terminal connected to the first node; means for varying the VBE voltage drop of said first transistor in accordance with whether the voltage level of the first voltage supply is above or below a threshold voltage and for continuously sinking current from said first transistor; and means for varying the voltage level at the current-emitting terminal of the first transistor to counteract, in combination with the varying VBE voltage drop, the change in the voltage level of the first voltage supply.
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公开(公告)号：DE3682043D1
公开(公告)日：1991-11-21
申请号：DE3682043
申请日：1986-12-02
Applicant: IBM
IPC: H03K19/0175 , H03K17/16 , H03K19/003 , H03K19/018 , H03K19/0185 , H03K19/088 , H03K5/02
Abstract: A small signal swing line driver (100), that generates a reduced amount of switching noise and also suppresses transients appearing on the line, is described. Specifically, the driver (100) includes a clamp (200) connected to the driver output to limit the maximum DC driver output level and to suppress voltage transients, e.g. reflections, spikes or the like, appearing on the driven line and caused by conditions external to the driver (100). The driver (100) also contains circuitry to limit the transition times of the rising and falling edges of the driver output signal in order to reduce the amount of switching noise which is generated by the driver (100) and thereafter coupled onto quiet lines.
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公开(公告)号：BR8902365A
公开(公告)日：1990-01-16
申请号：BR8902365
申请日：1989-05-23
Applicant: IBM
Inventor： GAUDENZI GENE JOSEPH
IPC: H03K17/04 , H03K19/013 , H03K19/082 , H03K19/086 , H03K3/33
Abstract: A circuit includes a set of seven NPN transistors (T1-T7), a Schottky diode (SD), and several resistors. The signal is connected from the input section to the output section directly from the base of a transistor (T2) in the input circuit to the base of the lower output transistor (T3), which (T2) is connected with its collector emitter connections in parallel with the emitter resistor (R3) of the input transistors which receive the input signals to the circuit. Two transistors (T1,T6) are connected to input terminals to provide a possible NOR arrangement although one of them alone can be used if the requirement of the circuit is simply for an inverter circuit. The output transistors comprise a push-pull output section (T3,T4).
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公开(公告)号：SG44402A1
公开(公告)日：1997-12-19
申请号：SG1996000189
申请日：1989-04-11
Applicant: IBM
Inventor： BLAND PATRICK MAURICE , DEAN MARK EDWARD , GAUDENZI GENE JOSEPH , KRAMER KEVIN GERRARD , TEMPEST SUSAN LYNN
Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes : a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data patch comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanism for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.
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公开(公告)号：CA1338155C
公开(公告)日：1996-03-12
申请号：CA596778
申请日：1989-04-14
Applicant: IBM
Inventor： BLAND PATRICK MAURICE , DEAN MARK EDWARD , GAUDENZI GENE JOSEPH , KRAMER KEVIN GERRARD , TEMPEST SUSAN LYNN
Abstract: A circuit for buffering and parity checking digital data communicated between first and second data buses includes a plurality of bidirectional bit buffer circuits. Each of the bidirectional bit buffer circuits includes: a first data path comprising a data receiver, latch, and driver connected in series between the first and second data buses, respectively; a second data path comprising a data receiver, latch and driver connected in series between the second and first data buses, respectively; control mechanisms for controlling the drivers to selectively place the output of the drivers in an active driving or high impedance state; and control mechanisms for controlling the data latches to selectively latch or pass through data. A parity generating circuit is connected at the output of the latch in the first data path of each of the bidirectional bit buffer circuits for generating a parity bit responsive to the data at the output of these latches. A transparent latch and driver circuit with phase splitter are provided for increasing the speed of the circuit without substantially increasing the power requirements.
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