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    OPTICAL MEMORY DEVICE
    11.
    发明专利
    OPTICAL MEMORY DEVICE 失效

    公开(公告)号：JPH10177721A

    公开(公告)日：1998-06-30

    申请号：JP31361897

    申请日：1997-11-14

    Applicant: IBM

    Inventor： BRADY MICHAEL J ,  BRAREN BODIL E ,  GAMBINO RICHARD J ,  GRILL ALFRED ,  PATEL VISHNUBHAI V

    IPC: B41M5/26 ,  G11B7/00 ,  G11B7/0045 ,  G11B7/0055 ,  G11B7/24 ,  G11B7/243 ,  G11B7/258 ,  G11B7/30

    Abstract: PROBLEM TO BE SOLVED: To obtain an optical memory medium based on completely novel memory principle and to obtain an optical memory device using this medium by recording data corresponding to characteristics of an amorphous solid selected from a group of materials each having refractive index and reflectance. SOLUTION: The amorphous solid is selected from a group of diamond-like carbon, silicon carbide, boron carbide, boron nitride, amorphous silicon and amorphous germanium, and the solid contains hydrogen by up to 50 atm% with covalent bonds. A specified region of the amorphous solid having a first refractive index and having atoms with covalent bonds is heated with laser light to change the refractive index in the heated area to a second refractive index. Thus, two states can be produced to correspond the memory of data without dissolving or crystallizing the amorphous solid. The density of the solid is changed by heating, which accompanies changes in the refractive index and reflectance.

    STRUCTURE FOR AND METHOD OF FABRICATING A HIGH-SPEED CMOS-COMPATIBLE Ge-ON-INSULATOR PHOTODETECTOR
    12.
    发明申请
    STRUCTURE FOR AND METHOD OF FABRICATING A HIGH-SPEED CMOS-COMPATIBLE Ge-ON-INSULATOR PHOTODETECTOR 审中-公开
    高速CMOS兼容绝缘栅双极型晶体管的结构和制作方法

    公开(公告)号：WO2005083750A3

    公开(公告)日：2005-10-27

    申请号：PCT/US2005005570

    申请日：2005-02-22

    Applicant: IBM ,  CHU JACK O ,  DEHLINGER GABRIEL K ,  GRILL ALFRED ,  KOESTER STEVEN J ,  OUYANG QIGING ,  SCHAUB JEREMY D

    Inventor： CHU JACK O ,  DEHLINGER GABRIEL K ,  GRILL ALFRED ,  KOESTER STEVEN J ,  OUYANG QIGING ,  SCHAUB JEREMY D

    IPC: H01L31/101

    CPC classification number: H01L31/101

    Abstract: The invention addresses the problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology. The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n-­and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing a Ge absorbing layer, low voltage operation by utilizing thin a absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of a group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

    Abstract translation: 本发明解决了创建与Si CMOS技术兼容的高速，高效率光电探测器的问题。 该结构由薄SOI衬底上的Ge吸收层组成，并利用隔离区，交替的n型和p型触点以及低电阻表面电极。 该器件利用掩埋绝缘层隔离底层衬底中产生的载流子，通过利用Ge吸收层在广谱上获得高量子效率，利用薄吸收层和窄电极间距实现低电压操作，以及兼容性 凭借其平面结构和使用IV族吸收材料而具有CMOS器件。 用于制造光电检测器的方法使用在薄SOI或外延氧化物上直接生长Ge，并且随后进行热退火以实现高质量的吸收层。 该方法限制了可用于相互扩散的Si的量，由此允许Ge层退火而不会导致Ge层基本上被下面的Si稀释。

    RELAXED SiGe LAYERS ON Si OR SILICON-ON-INSULATOR SUBSTRATES BY ION IMPLANTATION AND THERMAL ANNEALING
    13.
    发明申请
    RELAXED SiGe LAYERS ON Si OR SILICON-ON-INSULATOR SUBSTRATES BY ION IMPLANTATION AND THERMAL ANNEALING 审中-公开
    通过离子植入和热退火在Si或硅绝缘体衬底上放置SiGe层

    公开(公告)号：WO2004047150A3

    公开(公告)日：2004-06-24

    申请号：PCT/US0336969

    申请日：2003-11-19

    Applicant: IBM ,  CHRISTIANSEN SILKE H ,  CHU JACK O ,  GRILL ALFRED ,  MOONEY PATRICIA M

    Inventor： CHRISTIANSEN SILKE H ,  CHU JACK O ,  GRILL ALFRED ,  MOONEY PATRICIA M

    IPC: H01L21/20 ,  H01L21/265 ,  H01L21/762 ,  H01L21/302 ,  H01L21/461

    CPC classification number: H01L21/26506 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/02667 ,  H01L21/02694 ,  H01L21/7624 ,  H01L21/76251 ,  Y10S438/933

    Abstract: A method to obtain thin (less than 300 nm) strain-relaxed Si1-xGex buffer layers on Si or silicon-on-insulator (SOI) substrates. These buffer layers have a homogeneous distribution of misfit dislocations that relieve the strain, remarkably smooth surfaces, and a low threading dislocation (TD) density, i.e. less than 10 cm . The approach begins with the growth of a pseudomorphic or nearlypseudomorphic Si1-xGex layer, i.e., a layer that is free of misfit dislocations, which is then implanted with He or other light elements and subsequently annealed to achieve the substantial strain relaxation. The very effective strain relaxation mechanism operatiing with this method is dislocation nucleation at He-inducedplatelets (not bubbles) that lie below the Si/Si1-xGex interface, parallel to the Si(001) surface.

    Abstract translation: 在Si或绝缘体上硅（SOI）衬底上获得薄（小于300nm）应变弛豫Si1-xGex缓冲层的方法。 这些缓冲层具有失配位错的均匀分布，其缓解了应变，表面光滑平滑，以及低穿透位错（TD）密度，即小于10 6 cm 2。 该方法开始于伪晶体或近似假晶Si1-xGex层的生长，即，不具有失配位错的层，然后将其注入He或其它轻元素，随后退火以实现实质的应变弛豫。 用这种方法操作的非常有效的应变松弛机理是位于Si（001）表面Si / Si1-xGex界面以下的He诱导的电镀层（不是气泡）的位错成核。

    STRUCTURE FOR AND METHOD OF FABRICATING HIGH-SPEED CMOS-COMPATIBLE Ge-ON-INSULATOR PHOTODETECTOR
    14.
    发明专利
    STRUCTURE FOR AND METHOD OF FABRICATING HIGH-SPEED CMOS-COMPATIBLE Ge-ON-INSULATOR PHOTODETECTOR 有权
    制造高速CMOS兼容Ge-ON-INSULATOR PHOTODETECTOR的结构与方法

    公开(公告)号：JP2012186507A

    公开(公告)日：2012-09-27

    申请号：JP2012138161

    申请日：2012-06-19

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： CHU JACK O ,  DELLINGER GABRIEL K ,  GRILL ALFRED ,  STEVEN J KOESTER ,  QIGING OUYANG ,  JEREMY D SCHAUB

    IPC: H01L31/10 ,  H01L27/146 ,  H01L31/101

    CPC classification number: H01L31/101

    Abstract: PROBLEM TO BE SOLVED: To address a problem of creating a high-speed, high-efficiency photodetector that is compatible with Si CMOS technology.SOLUTION: The structure consists of a Ge absorbing layer on a thin SOI substrate, and utilizes isolation regions, alternating n- and p-type contacts, and low-resistance surface electrodes. The device achieves high bandwidth by utilizing a buried insulating layer to isolate carriers generated in the underlying substrate, high quantum efficiency over a broad spectrum by utilizing the Ge absorbing layer, low voltage operation by utilizing a thin absorbing layer and narrow electrode spacings, and compatibility with CMOS devices by virtue of its planar structure and use of the group IV absorbing material. The method for fabricating the photodetector uses direct growth of Ge on thin SOI or an epitaxial oxide, and subsequent thermal annealing to achieve a high-quality absorbing layer. This method limits the amount of Si available for interdiffusion, thereby allowing the Ge layer to be annealed without causing substantial dilution of the Ge layer by the underlying Si.

    Abstract translation: 要解决的问题：解决与Si CMOS技术兼容的高速，高效率光电探测器的问题。 解决方案：该结构由薄SOI衬底上的Ge吸收层组成，并且利用隔离区，交替的n型和p型接触以及低电阻表面电极。 该器件利用掩埋绝缘层，通过利用Ge吸收层，通过利用薄吸收层和窄电极间距的低电压操作以及兼容性来兼容宽泛的光谱，利用掩埋绝缘层隔离下层衬底中产生的载流子，获得高量子效率 其CMOS器件凭借其平面结构和IV族吸收材料的使用。 用于制造光电检测器的方法使用在薄SOI或外延氧化物上的Ge的直接生长，以及随后的热退火以实现高质量的吸收层。 该方法限制可用于相互扩散的Si的量，从而允许Ge层退火，而不会导致Ge层被下面的Si大量稀释。 版权所有（C）2012，JPO＆INPIT

    Semiconductor structure with improved bonding interface on carbon-based material, method for forming the same, and electronic device
    15.
    发明专利
    Semiconductor structure with improved bonding interface on carbon-based material, method for forming the same, and electronic device 审中-公开
    具有改进的基于碳的材料的接合界面的半导体结构，其形成方法和电子器件

    公开(公告)号：JP2011211175A

    公开(公告)日：2011-10-20

    申请号：JP2011044902

    申请日：2011-03-02

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： NGUYEN SON VAN ,  GRILL ALFRED ,  GATES STEPHEN M ,  VO TUAN ANH ,  DIMITRAKOPOULOS CHRISTOS ,  NEUMAYER DEBORAH ANN ,  DAMON B FARMER

    IPC: H01L29/78 ,  H01L21/28 ,  H01L29/786

    CPC classification number: H01L29/1606 ,  H01L29/7781 ,  H01L29/78 ,  H01L29/7831

    Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor structure and electronic device, formed in high density, and having smaller structural dimensions and a more exact shape.SOLUTION: Semiconductor structures and electronic devices include at least one layer of an interfacial dielectric material located on an upper surface of a carbon-based material. The at least one layer of interfacial dielectric material has a short-range crystallographic bonding structure, typically hexagonal, that is the same as that of the carbon-based material and, as such, the at least one layer of interfacial dielectric material does not change the electronic structure of the carbon-based material. The presence of the at least one layer of interfacial dielectric material having the same short-range crystallographic bonding structure as that of the carbon-based material improves the interfacial bonding between the carbon-based material and any overlying material layer, including a dielectric material, a conductive material or a combination of a dielectric material and a conductive material. The improved interfacial bonding in turn facilitates formation of devices including a carbon-based material.

    Abstract translation: 要解决的问题：提供一种形成为高密度且具有较小结构尺寸和更精确形状的半导体结构和电子器件。解决方案：半导体结构和电子器件包括至少一层界面介电材料，位于 碳基材料的上表面。 所述至少一层界面介电材料具有与碳基材料相同的短程结晶结合结构，通常是六边形，因此至少一层界面介电材料不会改变 碳基材料的电子结构。 具有与碳基材料相同的短程结晶结合结构的至少一层界面介电材料的存在改善了碳基材料和任何覆盖材料层（包括介电材料）之间的界面结合， 导电材料或介电材料和导电材料的组合。 改进的界面结合又有助于形成包括碳基材料的装置。

    Ultralow dielectric constant material as an intra-level or inter-level dielectric in semiconductor device
    18.
    发明专利
    Ultralow dielectric constant material as an intra-level or inter-level dielectric in semiconductor device 审中-公开
    超导介电常数材料作为半导体器件中的级内或层间电介质

    公开(公告)号：JP2011119770A

    公开(公告)日：2011-06-16

    申请号：JP2011052860

    申请日：2011-03-10

    Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

    Inventor： GRILL ALFRED ,  PATEL VISHNUBHAI V

    IPC: H01L21/312 ,  H01L21/768 ,  C23C16/30 ,  C23C16/40 ,  H01L21/316 ,  H01L23/522 ,  H01L23/532

    CPC classification number: C23C16/401 ,  H01L21/02126 ,  H01L21/02216 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/3122 ,  H01L21/31633 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: PROBLEM TO BE SOLVED: To provide an ultralow dielectric material having an dielectric constant of approximate 2.6 or less and a method for preparing the same. SOLUTION: A thermally stable ultralow dielectric constant film, which contains an Si atom, C atom, O atom, and H atom, has a covalent bond three dimensional network structure, and has a dielectric constant of 2.6 or less, is provided. Moreover, the dielectric constant film can have a covalent bond ring network too. The covalent bond three dimensional network structure includes an Si-O covalent bond, Si-C bond, Si-H bond, C-H covalent bond, and C-C covalent bond, and if necessary, it can include an F and N. On the film, if necessary, a Ge atom is substituted for a part of the Si atom. The film has a thickness of 1.3 micrometer or less and has a crack growth rate in water of 10 -10 meter/sec or less. Moreover, a back end of line (BEOL) mutual connection structure including the film as a BEOL insulator, cap, or hard mask layer is provided too. COPYRIGHT: (C)2011,JPO&INPIT

    Abstract translation: 要解决的问题：提供介电常数为2.6或更小的超低介电材料及其制备方法。 解决方案：提供含有Si原子，C原子，O原子和H原子的热稳定的超低介电常数膜，具有共价键三维网络结构，并且具有2.6以下的介电常数 。 此外，介电常数膜也可以具有共价键环网络。 共价键三维网络结构包括Si-O共价键，Si-C键，Si-H键，CH共价键和CC共价键，如果需要，它可以包括F和N.在薄膜上， 如果需要，用锗原子代替一部分Si原子。 该膜的厚度为1.3微米以下，水的裂纹生长率为10 -10秒/秒以下。 此外，还提供了包括作为BEOL绝缘体，帽或硬掩模层的膜的线后端（BEOL）相互连接结构。 版权所有（C）2011，JPO＆INPIT

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