公开(公告)号：IT1162577B

公开(公告)日：1987-04-01

申请号：IT2532879

申请日：1979-08-29

Applicant: IBM

Inventor： CLEMEN RAINER ,  GSCHWENDTNER JOERG ,  HAUG WERNER

IPC: G11C11/41 ,  G11C11/24 ,  G11C11/408 ,  G11C11/413 ,  H03K3/353 ,  H03K3/356 ,  H03K5/02 ,  H03K5/15 ,  H03K19/0185 ,  H03K

Abstract: Disclosed is a field effect transistor (FET) circuit for accepting a bipolar transistor logic level input signal and providing FET logic level output signals (both in-phase and out-of-phase components). The FET circuit includes a gated latch with means for pre-charging first and second nodes to an FET logic up level. One of the two nodes is brought to a slightly higher or lower level (depending on the binary value of the input), thereby producing a latent imbalance in the latch. A gating signal causes the latch to switch into the state pre-set by the latent imbalance.

公开(公告)号：CA951384A

公开(公告)日：1974-07-16

申请号：CA145360

申请日：1972-06-22

Applicant: IBM

Inventor： BAITINGER UTZ ,  HAUG WERNER

IPC: H03K5/02 ,  H03K19/017 ,  H03K19/0944 ,  H03K19/096

Abstract: Disclosed is an inverter circuit consisting of a first field-effect transistor connected in series to a capacitive load and a second field-effect transistor connected in parallel to said load, whereby charging and discharging of the capacitive load are effected via the first and second field-effect transistor, respectively, and a defined potential is applied to the capacitive load via a third field-effect transistor when the first field-effect transistor is inhibited.

公开(公告)号：DE2964606D1

公开(公告)日：1983-03-03

申请号：DE2964606

申请日：1979-07-16

Applicant: IBM

Inventor： GSCHWENDTNER JORG ,  HAUG WERNER ,  CLEMEN RAINER

IPC: G11C11/41 ,  G11C11/24 ,  G11C11/408 ,  G11C11/413 ,  H03K3/353 ,  H03K3/356 ,  H03K5/02 ,  H03K5/15 ,  H03K19/0185

Abstract: Disclosed is a field effect transistor (FET) circuit for accepting a bipolar transistor logic level input signal and providing FET logic level output signals (both in-phase and out-of-phase components). The FET circuit includes a gated latch with means for pre-charging first and second nodes to an FET logic up level. One of the two nodes is brought to a slightly higher or lower level (depending on the binary value of the input), thereby producing a latent imbalance in the latch. A gating signal causes the latch to switch into the state pre-set by the latent imbalance.

公开(公告)号：FR2295527A1

公开(公告)日：1976-07-16

申请号：FR7533269

申请日：1975-10-20

Applicant: IBM

Inventor： BAITINGER UTZ DR ,  NAJMANN KNUT ,  HAUG WERNER

IPC: G11C11/411 ,  H01L21/8229 ,  H01L27/07 ,  H01L27/102 ,  G11C11/40

Abstract: A semiconductor storage circuit for use in monolithic memories. The circuit is comprised of a storage cell coupled to input-output bit lines through active devices having symmetrical conduction properties. The storage cell can be comprised of a pair of cross coupled bipolar transistors having resistors as collector load devices. Schottky field effect transistors (MESFET's) are active devices having symmetrical conduction properties.