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公开(公告)号：AU1406901A
公开(公告)日：2001-06-04
申请号：AU1406901
申请日：2000-11-21
Inventor： AYDEMIR METIN , BASS BRIAN MITCHELL , JEFFRIES CLARK DEBS , ROVNER SONIA KIANG , SIEGEL MICHAEL STEVEN , GALLO ANTHONY MATTEO , GORTI BRAHMANAND KUMAR , HEDDES MARCO
Abstract: Methods, apparatus and program products for controlling a flow of a plurality of packets in a computer network are disclosed. The computer network includes a device defining a queue. The methods, apparatus and program products include determining a queue level for the queue and determining an offered rate of the plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, based on the queue level, the offered rate and a previous value of the transmission fraction so that the transmission fraction and the queue level are critically damped if the queue level is between at least a first queue level and a second queue level. Several embodiments are disclosed in which various techniques are used to determine the manner of the control.
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公开(公告)号：HU0203928A2
公开(公告)日：2003-04-28
申请号：HU0203928
申请日：2000-11-21
Inventor： AYDEMIR METIN , BASS BRIAN MITCHELL , GALLO ANTHONY MATTEO , GORTI BRAHMANAND KUMAR , HEDDES MARCO , JEFFRIES CLARK DEBS , ROVNER SONIA KIANG , SIEGEL MICHAEL STEVEN
Abstract: Methods, apparatus and program products for controlling a flow of a plurality of packets in a computer network are disclosed. The computer network includes a device defining a queue. The methods, apparatus and program products include determining a queue level for the queue and determining an offered rate of the plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, based on the queue level, the offered rate and a previous value of the transmission fraction so that the transmission fraction and the queue level are critically damped if the queue level is between at least a first queue level and a second queue level. Several embodiments are disclosed in which various techniques are used to determine the manner of the control.
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公开(公告)号：DE60210748T2
公开(公告)日：2007-01-04
申请号：DE60210748
申请日：2002-02-20
Applicant: IBM
Inventor： CALVIGNAC LOUIS , HEDDES MARCO , LOGAN FRANKLIN , VERPLANKEN JEAN
Abstract: A method and system for reducing memory accesses by inserting qualifiers in control blocks. In one embodiment, a system comprises a processor configured to process frames of data. The processor may comprise a plurality of buffers configured to store frames of data where each frame of data may be associated with a frame control block. Each frame control block associated with a frame of data may be associated with one or more buffer control blocks. Each control block, e.g., frame control block, buffer control block, may comprise one or more qualifier fields that comprise information unrelated to the current control block. Instead, qualifiers may comprise information related to an another control block. The last frame control block in a queue as well as the last buffer control block associated with a frame control block may comprise fields with no information thereby reducing memory accesses to access information in those fields.
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公开(公告)号：AT293864T
公开(公告)日：2005-05-15
申请号：AT02712095
申请日：2002-02-20
Applicant: IBM
Inventor： CALVIGNAC JEAN LOUIS , HEDDES MARCO , PARK WINCHESTER , LOGAN JOSEPH FRANKLIN , VERPLANKEN FABRICE JEAN
IPC: H04L12/861 , H04L29/06 , H04L12/56
Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.
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公开(公告)号：DE60109215D1
公开(公告)日：2005-04-07
申请号：DE60109215
申请日：2001-09-27
Applicant: IBM
Inventor： DAMON PHILIPE , HEDDES MARCO
Abstract: A timer management system and method for managing timers in both a synchronous and asynchronous system. In one embodiment of the present invention, a timer management system comprises an application program interface (API) for providing a set of synchronous functions allowing an application to functionally operate on the timer. The timer management system further comprises a timer database for storing timer-related information. Furthermore, the timer management system comprises a timer services for detecting the expiring of the timer. A handle function of the timer services allows an asynchronous application, i.e., application in a multi-task system, to synchronously act on the timer. That is, when a timer in a asynchronous system times-out, the handle function allows the asynchronous application to act on the expired timer without incurring an illegal time-out message. In another embodiment of the present invention, a timer may be reinitialized from the same allocated block of memory used to create the timer. In another embodiment of the present invention, a time-out message may be sent using the same allocated block of memory used to create the timer.
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Patent Agency Ranking
公开(公告)号：ES2226958T3
公开(公告)日：2005-04-01
申请号：ES00983409
申请日：2000-12-21
Applicant: IBM
Inventor： BASS BRIAN MITCHELL , CALVIGNAC JEAN LOUIS , DAVIS GORDON TAYLOR , GALLO ANTHONY MATTEO , HEDDES MARCO , JENKINS STEVEN KENNETH
Abstract: Un aparato que comprende: un substrato semiconductor; N unidades (110) de procesamiento fabricadas sobre el substrato, donde N > 1; una primera memoria de datos interna accesible para dichas N unidades de procesamiento; una unidad (112) de expedición acoplada operativamente a las N unidades de procesamiento para recibir y transmitir una unidad de información de entrada a una de las N unidades de procesamiento; una unidad (118) de clasificación acoplada a la unidad (112) de expedición, incluyendo dicha unidad de clasificación una unidad (114) de comparación para determinar un formato de datos para una unidad de información de entrada y para generar y almacenar en la memoria de datos interna indicadores de salida para la unidad de información de entrada, que indican el formato de datos de la unidad de información de entrada y una dirección de arranque para la unidad de información de entrada, cuyos indicadores y dirección de arranque están disponibles para una de las N unidades de procesamiento durante su procesamiento de la unidad de información de entrada y son utilizados en el procesamiento de la unidad de información de entrada; y una unidad (114) de compleción soportada en el substrato semiconductor y conectada operativamente a las N unidades (110) de procesamiento para recibir la unidad de información procesada por la unidad considerada de las N unidades (110) de procesamiento.
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公开(公告)号：HU0303240A2
公开(公告)日：2003-12-29
申请号：HU0303240
申请日：2002-02-20
Applicant: IBM
Inventor： CALVIGNAC JEAN LOUIS , HEDDES MARCO , LOGAN JOSEPH FRANKLIN , VERPLANKEN FABRICE JEAN
IPC: H04L12/861 , H04L29/06
Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.
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公开(公告)号：AU2002232002A1
公开(公告)日：2002-09-12
申请号：AU2002232002
申请日：2002-02-20
Applicant: IBM
Inventor： CALVIGNAC JEAN LOUIS , LOGAN JOSEPH FRANKLIN , HEDDES MARCO , VERPLANKEN FABRICE JEAN
IPC: H04L12/861 , H04L29/06
Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.
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公开(公告)号：CA2387101A1
公开(公告)日：2001-05-31
申请号：CA2387101
申请日：2000-11-21
Applicant: IBM
Inventor： AYDEMIR METIN , GORTI BRAHMANAND KUMAR , HEDDES MARCO , BASS BRIAN MITCHELL , JEFFRIES CLARK DEBS , ROVNER SONIA KIANG , GALLO ANTHONY MATTEO , SIEGEL MICHAEL STEVEN
Abstract: Methods, apparatus and program products for controlling a flow of a pluralit y of packets in a computer network are disclosed. The computer network include s a device defining a queue. The methods, apparatus and program products inclu de determining a queue level for the queue and determining an offered rate of t he plurality of packets to the queue. They also include controlling a transmission fraction of the plurality of packets to or from the queue, base d on the queue level, the offered rate and a previous value of the transmissio n fraction so that the transmission fraction and the queue level are criticall y damped if the queue level is between at least a first queue level and a seco nd queue level. Several embodiments are disclosed in which various techniques a re used to determine the manner of the control.
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公开(公告)号：DE69129851D1
公开(公告)日：1998-08-27
申请号：DE69129851
申请日：1991-09-13
Applicant: IBM
Inventor： HEDDES MARCO , LUIJTEN RONALD PETER
Abstract: The present invention relates to a data transmission system and concerns a method for transforming user frames into fixed length cells, e.g. ATM (Asynchronous Transfer Mode), such that the fixed length cells can be transported through a cell handling switch fabric (11). A hardware implementation of this method consists of two parts, a transmitter (12.1) and a receiver (13.1), both being part of a switching subsystem (10) comprising a switch fabric (11). The transmitter (12.1) buffers user data and segments them into fixed length cells to be transported through said switch (11). The receiver part (13.1) reassembles user data on reception of these cells.
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