公开(公告)号：CA1097810A

公开(公告)日：1981-03-17

申请号：CA272815

申请日：1977-02-28

Applicant: IBM

Inventor： HELLER LAWRENCE G ,  TERMAN LEWIS M

IPC: H03M1/44 ,  G11C11/56 ,  G11C19/18 ,  G11C19/36 ,  G11C27/02 ,  H03K4/02 ,  H03M1/00 ,  H03M1/66 ,  G11C11/40

Abstract: CHARGE-TRANSFER BINARY SEARCH GENERATING CIRCUIT A bucket brigade circuit is described for generating a sequence of packets of charge carriers of the form QR/2, QR/4, QR/8....QR/2N where N is an integer. The charge packets thus generated can be employed in combinations in either digital-to-analog or analog-to-digital converters. The charge generation circuit requires two equal capacitors which are used for charge redistribution. To obtain accurate quantities of charge in the generated charge packets the capacitors employed should be large, however the use of large capacitors results in low operating speed because of the large charge transfer time constants involved. The described circuit provides a scheme to reduce charge transfer time constants and therefore obtain greater speed while still permitting the use of large capacitors for high accuracy. The circuit includes a small coupling capacitor connected in series with one of the charge redistribution capacitors to produce a total capacitance which is equal to or smaller than the coupling capacitance. The sequence of charge carriers produced by the circuit can be injected into either a bucket brigade circuit or a charge-coupled-device circuit for use, for example, in digital-to-analog and analog-to-digital converters.

公开(公告)号：CA1072644A

公开(公告)日：1980-02-26

申请号：CA278859

申请日：1977-05-20

Applicant: IBM

Inventor： HELLER LAWRENCE G ,  TERMAN LEWIS M ,  YEE YEN S

IPC: G01R19/165 ,  H03K3/353 ,  H03K3/356 ,  H03K5/08 ,  H03K5/24 ,  H03K5/20

Abstract: HIGH ACCURACY MOS COMPARATOR The voltages to be compared are applied to a passive MOS capacitor differencing circuit for producing a voltage difference signal, which then is amplified by a high-gain non-precision FET amplifier, the output of which is passed through a low output impedance FET buffer amplifier to an FET latching circuit. Capacitive coupling is used for enabling the amplifiers to be independently biased and to eliminate D.C. offsets. The operating cycle of the comparator has two periods. During an initial set-up or preconditioning period the amplifiers are self-biased by appropriate switching actions which cause each of the amplifiers to be set at a desired operating point that is maintained when its respective bias switching connection subsequently is opened. The bias switch openings in the respective amplifier and latching stages are timed to occur in a chosen sequence which causes the switching transients to be absorbed. At the end of the preconditioning period, the comparator is set up for operation in the comparison period during which the input signals are compared.

公开(公告)号：FR2345788A1

公开(公告)日：1977-10-21

申请号：FR7703515

申请日：1977-02-01

Applicant: IBM

Inventor： HELLER LAWRENCE G ,  TERMAN LEWIS M

IPC: H03M1/44 ,  G11C11/56 ,  G11C19/18 ,  G11C19/36 ,  G11C27/02 ,  H03K4/02 ,  H03M1/00 ,  H03M1/66 ,  G11C19/28 ,  H03K13/02

Abstract: A bucket brigade circuit is described for generating a sequence of packets of charge carriers of the form QR/2, QR/4, QR/8....QR/2N where N is an integer. The charge packets thus generated can be employed in combinations in either digital-to-analog or analog-to-digital converters. The charge generation circuit requires two equal capacitors which are used for charge redistribution. To obtain accurate quantities of charge in the generated charge packets the capacitors employed should be large, however the use of large capacitors results in low operating speed because of the large charge transfer time constants involved. The described circuit provides a scheme to reduce charge transfer time constants and therefore obtain greater speed while still permitting the use of large capacitors for high accuracy. The circuit includes a small coupling capacitor connected in series with one of the charge redistribution capacitors to produce a total capacitance which is equal to or smaller than the coupling capacitance. The sequence of charge carriers produced by the circuit can be injected into either a bucket brigade circuit or a charge-coupled-device circuit for use, for example, in digital-to-analog and analog-to-digital converters.

公开(公告)号：CA1100638A

公开(公告)日：1981-05-05

申请号：CA272261

申请日：1977-02-21

Applicant: IBM

Inventor： HELLER LAWRENCE G ,  TERMAN LEWIS M

IPC: H03M1/44 ,  H01L29/768 ,  H01L29/78 ,  H03M1/00 ,  H03K13/03

Abstract: ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTER CIRCUITS EMPLOYING CHARGE REDISTRIBUTION Analog-to-digital (A/D) and digital-to-analog (D/A) converter circuits are provided using charge redistribution. The analog-to-digital converter circuit also employs successive approximation binary search techniques wherein the number of search voltages generated is a minimum. The analog-to-digital circuit includes a digital-to-analog converter circuit, a comparator circuit and a logic control means. The digital-to-analog circuit, under control of the logic means, accepts a reference voltage input and produces a sequence of search voltages which are compared with an unknown analog input voltage at the comparator. The resultant outputs from the comparator are applied to the control logic to determine the search voltage sequence. The digital-to-analog converter for the aforesaid circuit is provided in one embodiment employing charge-coupled-device technology. A substrate and two storage electrodes are combined to produce two potential storage wells and a transfer electrode is provided to move charge carriers between the storage wells. A reference charge packet QR is stored and divided by charge redistribution between the two potential wells to produce a sequence of charge packets of value QR/2, QR/4, QR/8, QR/16 etc. which can be selectively combined to produce analog output of a D/A converter. In the A/D converter the same sequence of charge packets is used to generate the equivalent of a binary search sequence QR/2, QR?QR/4, ?QR/8 etc. In another embodiment a bucket brigade device is provided to accomplish the same result. Because of the technique of charge redistribution wherein precise amounts of charge can be shifted in either direction between storage means, the total number of search value steps is a minimum. YO975-017 -1-

公开(公告)号：CA1099409A

公开(公告)日：1981-04-14

申请号：CA293097

申请日：1977-12-14

Applicant: IBM

Inventor： HELLER LAWRENCE G ,  TERMAN LEWIS M ,  YEE YEN S

IPC: G01R19/10 ,  G01R29/24 ,  G11C27/04 ,  H01L21/339 ,  H01L29/762 ,  H01L29/768 ,  H03M1/00 ,  G11C11/08

Abstract: CHARGE TRANSFER DEVICE DIFFERENCING CIRCUIT A circuit is disclosed for obtaining an output signal proportional to the difference between two charge packet quantities nondestructively. The preferred embodiment includes a substrate with a potential well disposed under a floating gate electrode having charge transfer means for entering and removing charge from the potential well. A first quantity of charge Qa which is stored in the potential well is transferred out of the well at time t1 with a resulting proportional increase in the floating gate voltage which results from capacitor coupling from the charge to the floating gate. At a subsequent time t2 a second charge quantity Qb is transferred into the potential well and causes a proportional decrease in the floating gate voltage. The net change .DELTA.V in the floating gate voltage that results is proportional to the difference between the two charge quantities Q ant Qb.

公开(公告)号：FR2356319A1

公开(公告)日：1978-01-20

申请号：FR7716041

申请日：1977-05-17

Applicant: IBM

Inventor： HELLER LAWRENCE G ,  WHIT JAMES M

IPC: G06G7/19 ,  H03H15/02 ,  H03K ,  H03K5/159 ,  G11C19/28

Abstract: 1525352 Active filters INTERNATIONAL BUSINESS MACHINES CORP 27 April 1977 [25 June 1976] 17489/77 Heading H3U A charge transfer device (CTD) transversal filter includes two CTD's 10, 12 receiving respectively an analogue input signal and an analogue transfer function signal. The signals obtained at respective tapping points are summed by the gates of field effect transistors, the non-linear characteristic of which square the sums 16, 18. The transistor currents are then summed, 20, to provide either convolution or correlation depending on the relative directions of propagation of the two input signals along the CTD's. The arrangement may be implemented using either charge coupled or bucket brigade devices.

公开(公告)号：FR2343369A1

公开(公告)日：1977-09-30

申请号：FR7702067

申请日：1977-01-18

Applicant: IBM

Inventor： HELLER LAWRENCE G ,  TERMAN LEWIS M

IPC: H03M1/44 ,  H01L29/768 ,  H01L29/78 ,  H03M1/00 ,  H03K13/02

Abstract: Analog-to-digital (A/D) and digital-to-analog (D/A) converter circuits are provided using charge redistribution. The analog-to-digital converter circuit also employs successive approximation binary search techniques wherein the number of search voltages generated is a minimum. The analog-to-digital circuit includes a digital-to-analog converter circuit, a comparator circuit and a logic control means. The digital-to-analog circuit, under control of the logic means, accepts a reference voltage input and produces a sequence of search voltages which are compared with an unknown analog input voltage at the comparator. The resultant outputs from the comparator are applied to the control logic to determine the search voltage sequence. The digital-to-analog converter for the aforesaid circuit is provided in one embodiment employing charge-coupled-device technology. A substrate and two storage electrodes are combined to produce two potential storage wells and a transfer electrode is provided to move charge carriers between the storage wells. A reference charge packet QR is stored and divided by charge redistribution between the two potential wells to produce a sequence of charge packets of value QR/2, QR/4, QR/8, QR/16 etc. which can be selectively combined to produce analog output of a D/A converter. In the A/D converter the same sequence of charge packets is used to generate the equivalent of a binary search sequence QR/2, QR/2+/-QR/4, QR/2+/-QR/4+/-QR/8 etc. In another embodiment a bucket brigade device is provided to accomplish the same result. Because of the technique of charge redistribution wherein precise amounts of charge can be shifted in either direction between storage means, the total number of search value steps is a minimum.

公开(公告)号：FR2334171A1

公开(公告)日：1977-07-01

申请号：FR7632295

申请日：1976-10-21

Applicant: IBM

Inventor： HELLER LAWRENCE G

IPC: G11C7/02 ,  G11C19/28 ,  G11C27/04 ,  H01L21/339 ,  H01L29/762 ,  H01L29/768 ,  G11C9/06 ,  H01L27/06 ,  H01L29/40

Abstract: An input circuit for a charge-transfer-device such as a bucket-brigade or charge-coupled-device incorporating an input terminal connected to an input diode source diffusion of the charge-transfer-device through a capacitor C. The nonlinear depletion capacitance Cd associated with the input circuit is schematically shown connected in parallel with C at a first node. The non-linear capacitance Cd, which is parasitic, is a basic cause of distortion of the input charge packets. The input circuit further includes an active device such as an IGFET connected in parallel with the input terminal to provide a supply of charge carriers. The gate of the active device is connected to a reset signal source.

公开(公告)号：FR2329054A1

公开(公告)日：1977-05-20

申请号：FR7626316

申请日：1976-08-25

Applicant: IBM

Inventor： HELLER LAWRENCE G

IPC: H01L29/762 ,  G11C19/28 ,  H01L21/339 ,  H01L27/10 ,  H01L29/768 ,  H01L27/04

Abstract: A method and apparatus for duplicating or replicating an original packet of charge carriers such as electrons or holes while leaving the original charge packet unchanged and still available for further processing is described. A charge-coupled device (CCD) circuit is provided using gate displacement charge flow in combination with a bucket brigade circuit. The CCD circuit includes a first +CCD well, a source diffusion and a second CCD well. An original charge packet is introduced into the first CCD well, the gate of which being precharged to a given source potential. The charge packet in the first CCD well reduces the magnitude of the source potential and it is immediately restored by current flow which in turn causes charge carriers to transfer from the source diffusion into the second CCD well until a charge packet is contained in the second CCD well which is a replica of the original charge packet.

公开(公告)号：CA1099347A

公开(公告)日：1981-04-14

申请号：CA271023

申请日：1977-02-03

Applicant: IBM

Inventor： HELLER LAWRENCE G ,  SPAMPINATO DOMINIC P

IPC: G11C11/41 ,  G11C7/06 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  H03F3/45 ,  H03K3/356 ,  H03K5/20 ,  G11C11/40 ,  H03F3/16

Abstract: CROSS-COUPLED CHARGE TRANSFER SENSE AMPLIFIER CIRCUITS Sense amplifiers employing charge-transfer techniques and cross-coupled devices for use with memory cell arrays or as comparators, polarity sensors and differential amplifiers are described which include a unique preamplifier circuit having cross-coupled actuable devices and which provides a cross-coupled charge-transfer feature. The sense amplifier also includes actuable devices which provide further amplification. The preamplifier circuit includes two precharge actuable devices which have their gate electrode. connected to the phase 1 line and which have their source electrode connected through separate capacitors to the phase 2 line. The terminals of the two preamplifier charge-transfer devices which are cross-coupled are also connected at the aforesaid circuit nodes and to the bit/sense lines and to the further amplification devices. The disclosure describes two embodiments of a preamplifier circuit, each of which is shown in combination with a plurality of different further amplification circuits.