公开(公告)号：GB2508761B

公开(公告)日：2014-11-19

申请号：GB201404456

申请日：2012-09-13

Applicant: IBM

Inventor： FAINSTEIN DANIEL ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI

IPC: G11C29/00 ,  G06F21/44 ,  G06F21/73

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string that includes 2nd ID bit string. A retention pause time controls the number of retention fails, adjusted by a BIST engine, wherein the fail numbers satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

公开(公告)号：GB2508761A

公开(公告)日：2014-06-11

申请号：GB201404456

申请日：2012-09-13

Applicant: IBM

Inventor： FAINSTEIN DANIEL ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI

IPC: G11C29/00 ,  G06F21/44 ,  G06F21/73

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string 275 that includes 2nd ID bit string 290. A retention pause time controls the number of retention fails, adjusted by a BIST engine 625, wherein the fail numbers 803, 920 satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

公开(公告)号：CA2828498A1

公开(公告)日：2012-12-27

申请号：CA2828498

申请日：2012-06-19

Applicant: IBM

Inventor： ANDRY PAUL S ,  FAROOQ MUKTA G ,  HANNON ROBERT ,  IYER SUBRAMANIAN S ,  KINSER EMILY R ,  TSANG CORNELIA K ,  VOLANT RICHARD P

IPC: H01L21/28 ,  H01L21/768

Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.

公开(公告)号：DE60307793T2

公开(公告)日：2007-08-23

申请号：DE60307793

申请日：2003-02-27

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： IYER S SUNDAR K ,  IYER SUBRAMANIAN S ,  KOTHANDARAMAN CHANDRASEKHARAN ,  NARAYAN CHANDRASEKHAR

IPC: H01L23/525

Abstract: The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled to a power supply. A potential is applied across the conductive fuse link via the cathode and anode in which the potential is of a magnitude to initiate electromigration of silicide from a region of the semiconductor fuse reducing the conductivity of the fuse link. The electromigration is enhanced by effectuating a temperature gradient between the fuse link and one of the cathode and anode responsive to the applied potential. Portions of the semiconductor fuse are selectively cooled in a heat transfer relationship to increase the temperature gradient. In one embodiment, a heat sink is applied to the cathode. The heat sink can be a layer of metal coupled in close proximity to the cathode while insulated from the fuse link. In another embodiment, the temperature gradient is increased by selectively varying the thickness of the underlying oxide layer such that the cathode is disposed on a thinner layer of oxide than the fuse link.

公开(公告)号：DE102013224104A1

公开(公告)日：2014-06-12

申请号：DE102013224104

申请日：2013-11-26

Applicant: IBM

Inventor： CHELLAPPA SRIVATSAN ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI ,  ROSENBLATT SAMI

IPC: G06F21/44

Abstract: Ausführungsformen der vorliegenden Erfindung stellen einen Echtheitsnachweisdienst eines Chips bereit, der eine chipspezifische Kennung (ID) aufweist. Gemäß einer typischen Ausführungsform wird eine Echtheitsnachweiseinheit bereitgestellt, die ein Erkennungs-(ID-)Modul, ein Selbsttest-Modul und eine chipspezifische Komponente enthält. Die chipspezifische Komponente ist einem Chip zugehörig und enthält ein chipspezifisches Merkmal. Das Selbsttest-Modul ruft das chipspezifische Merkmal ab und übermittelt dieses an das Erkennungs-Modul. Das Erkennungs-Modul empfängt das chipspezifische Merkmal, erzeugt unter Verwendung des chipspezifischen Merkmals einen ersten Echtheitsnachweiswert und speichert den Echtheitsnachweiswert in einem Speicher. Das Selbsttest-Modul erzeugt unter Verwendung einer Echtheitsnachweisabfrage einen zweiten Echtheitsnachweiswert. Das Erkennungs-Modul enthält eine Vergleichsschaltung, die den ersten Echtheitsnachweiswert mit dem zweiten Echtheitsnachweiswert vergleicht und auf der Grundlage der Ergebnisse des Vergleichs der beiden Werte miteinander einen Echtheitsnachweis-Ausgabewert erzeugt.

公开(公告)号：DE112012001870T5

公开(公告)日：2014-03-27

申请号：DE112012001870

申请日：2012-06-19

Applicant: IBM

Inventor： FAROOQ MUKTA G ,  HANNON ROBERT ,  VOLANT RICHARD P ,  ANDRY PAUL S ,  IYER SUBRAMANIAN S ,  KINSER EMILY R ,  TSANG CORNELIA K

IPC: H01L21/28 ,  H01L21/768

Abstract: Die vorliegende Offenbarung stellt einen thermo-mechanisch zuverlässigen Kupfer-TSV sowie eine Technik zum Bilden eines derartigen TSV während eines BEOL-Prozessablaufs bereit. Der TSV bildet einen ringförmigen Graben, der sich durch das Halbleitersubstrat hindurch erstreckt. Das Substrat definiert die inneren und äußeren Seitenwände des Grabens, wobei die Seitenwände durch einen Abstand innerhalb des Bereichs von 5 bis 10 Mikrometer separiert sind. Ein leitfähiger Pfad, der Kupfer oder eine Kupfer-Legierung aufweist, erstreckt sich innerhalb des Grabens von einer oberen Fläche der ersten dielektrischen Schicht durch das Substrat hindurch. Die Dicke des Substrats kann 60 Mikrometer oder weniger betragen. Direkt über dem ringförmigen Graben ist eine dielektrische Schicht mit einer Zwischenverbindungsmetallisierung ausgebildet, die mit dem leitfähigen Pfad leitfähig verbunden ist.

公开(公告)号：CA2852883A1

公开(公告)日：2013-05-30

申请号：CA2852883

申请日：2012-09-13

Applicant: IBM

Inventor： FAINSTEIN DANIEL J ,  CESTERO ALBERTO ,  IYER SUBRAMANIAN S ,  KIRIHATA TOSHIAKI ,  ROSENBLATT SAMI ,  ROBSON NORMAN W

IPC: G11C29/00 ,  G06F21/00

Abstract: A random intrinsic chip ID generation employs a retention fail signature. A 1st and 2nd ID are generated using testing settings with a 1st setting more restrictive than the 2nd, creating more fails in the 1st ID bit string 275 that includes 2nd ID bit string 290. A retention pause time controls the number of retention fails, adjusted by a BIST engine 625, wherein the fail numbers 803, 920 satisfy a predetermined fail target. Verification confirms whether the 1st ID includes the 2nd ID bit string, the ID being the one used for authentication. Authentication is enabled by a 3rd ID with intermediate condition such that 1st ID includes 3rd ID bit string and 3rd ID includes 2nd ID bit string. The intermediate condition includes a guard-band to eliminate bit instability problem near the 1st and 2nd ID boundary. The intermediate condition is changed at each ID read operation, resulting in a more secure identification.

公开(公告)号：DE60307793D1

公开(公告)日：2006-10-05

申请号：DE60307793

申请日：2003-02-27

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： IYER S SUNDAR K ,  IYER SUBRAMANIAN S ,  KOTHANDARAMAN CHANDRASEKHARAN ,  NARAYAN CHANDRASEKHAR

IPC: H01L23/525

Abstract: The present invention provides a system, apparatus and method of programming via electromigration. A semiconductor fuse which includes a cathode and an anode coupled by a fuse link having an electrically conductive component, such as silicide, is coupled to a power supply. A potential is applied across the conductive fuse link via the cathode and anode in which the potential is of a magnitude to initiate electromigration of silicide from a region of the semiconductor fuse reducing the conductivity of the fuse link. The electromigration is enhanced by effectuating a temperature gradient between the fuse link and one of the cathode and anode responsive to the applied potential. Portions of the semiconductor fuse are selectively cooled in a heat transfer relationship to increase the temperature gradient. In one embodiment, a heat sink is applied to the cathode. The heat sink can be a layer of metal coupled in close proximity to the cathode while insulated from the fuse link. In another embodiment, the temperature gradient is increased by selectively varying the thickness of the underlying oxide layer such that the cathode is disposed on a thinner layer of oxide than the fuse link.