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公开(公告)号:WO2013066455A3
公开(公告)日:2014-05-08
申请号:PCT/US2012049414
申请日:2012-08-03
Applicant: IBM , COONEY EDWARD C , DUNN JAMES S , MARTIN DALE W , MUSANTE CHARLES F , RAINEY BETHANN , SHI LEATHEN , SPROGIS EDMUND J , TSANG CORNELIA K
Inventor: COONEY EDWARD C , DUNN JAMES S , MARTIN DALE W , MUSANTE CHARLES F , RAINEY BETHANN , SHI LEATHEN , SPROGIS EDMUND J , TSANG CORNELIA K
CPC classification number: H01L23/4825 , H01L21/6835 , H01L21/76819 , H01L22/32 , H01L22/34 , H01L23/5223 , H01L23/5283 , H01L24/02 , H01L24/03 , H01L24/05 , H01L24/06 , H01L24/08 , H01L24/13 , H01L24/16 , H01L24/80 , H01L24/81 , H01L29/1054 , H01L2221/68327 , H01L2221/6834 , H01L2221/68363 , H01L2221/68381 , H01L2224/0361 , H01L2224/0401 , H01L2224/05166 , H01L2224/05187 , H01L2224/05567 , H01L2224/05624 , H01L2224/05687 , H01L2224/06181 , H01L2224/08225 , H01L2224/131 , H01L2224/73251 , H01L2224/80011 , H01L2224/80013 , H01L2224/80075 , H01L2224/80203 , H01L2224/804 , H01L2224/80487 , H01L2224/80896 , H01L2224/80907 , H01L2224/80948 , H01L2224/81203 , H01L2224/81801 , H01L2224/81815 , H01L2924/00014 , H01L2924/12042 , H01L2924/1305 , H01L2924/1306 , H01L2924/13062 , H01L2924/15788 , H01L2924/014 , H01L2224/08 , H01L2224/16 , H01L2924/05432 , H01L2924/053 , H01L2924/01031 , H01L2924/01033 , H01L2924/04941 , H01L2924/00 , H01L2224/05552
Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures (18, 19, 20, 21) of a product chip (25) are formed using a first surface (15) of a device substrate (10). A wiring layer (26) of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer (52) is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface (54) of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate (56). The temporary handle wafer is then removed from the assembly.
Abstract translation: 用于粘合基板表面,粘合基板组件以及用于键合衬底组件的设计结构的方法。 使用器件衬底(10)的第一表面(15)形成产品芯片(25)的器件结构(18,19,20,21)。 在产品芯片上形成用于器件结构的互连结构的布线层(26)。 布线层被平坦化。 临时处理晶片(52)可移除地结合到平坦化的布线层。 响应于将临时手柄晶片可移除地结合到平坦化的第一布线层,与第一表面相对的器件基板的第二表面(54)被结合到最终的手柄基板(56)。 然后将临时手柄晶片从组件中取出。
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公开(公告)号:WO2012177585A3
公开(公告)日:2013-04-25
申请号:PCT/US2012043052
申请日:2012-06-19
Applicant: IBM , ANDRY PAUL S , FAROOQ MUKTA G , HANNON ROBERT , IYER SUBRAMANIAN S , KINSER EMILY R , TSANG CORNELIA K , VOLANT RICHARD P
Inventor: ANDRY PAUL S , FAROOQ MUKTA G , HANNON ROBERT , IYER SUBRAMANIAN S , KINSER EMILY R , TSANG CORNELIA K , VOLANT RICHARD P
IPC: H01L21/28 , H01L21/768
CPC classification number: H01L21/76846 , H01L23/481 , H01L2924/0002 , H01L2924/00
Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.
Abstract translation: 本公开提供了热机械可靠的铜TSV和在BEOL处理期间形成这种TSV的技术。 TSV构成延伸穿过半导体衬底的环形沟槽。 衬底限定沟槽的内侧壁和外侧壁,该侧壁分隔5至10微米的距离。 包括铜或铜合金的导电路径从所述第一介电层的上表面通过所述衬底在所述沟槽内延伸。 基板厚度可以为60微米或更小。 具有导电连接到导电路径的互连金属化的电介质层直接形成在所述环形沟槽上。
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公开(公告)号:GB2505576A
公开(公告)日:2014-03-05
申请号:GB201318982
申请日:2012-06-19
Applicant: IBM
Inventor: ANDRY PAUL S , FAROOQ MUKTA G , HANNON ROBERT , IYER SUBRAMANIAN S , KINSER EMILY R , TSANG CORNELIA K , VOLANT RICHARD P
IPC: H01L23/48 , H01L21/28 , H01L21/768
Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.
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公开(公告)号:GB2509683A
公开(公告)日:2014-07-09
申请号:GB201408711
申请日:2012-08-03
Applicant: IBM
Inventor: COONEY EDWARD C , DUNN JAMES S , MARTIN DALE W , MUSANTE CHARLES F , RAINEY BETH-ANN , SHI LEATHEN , SPROGIS EDMUND J , TSANG CORNELIA K
IPC: H01L23/522 , H01L21/768 , H01L23/528
Abstract: Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures (18, 19, 20, 21) of a product chip (25) are formed using a first surface (15) of a device substrate (10). A wiring layer (26) of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer (52) is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface (54) of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate (56). The temporary handle wafer is then removed from the assembly.
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公开(公告)号:GB2505576B
公开(公告)日:2016-03-23
申请号:GB201318982
申请日:2012-06-19
Applicant: IBM
Inventor: ANDRY PAUL S , FAROOQ MUKTA G , HANNON ROBERT , IYER SUBRAMANIAN S , KINSER EMILY R , TSANG CORNELIA K , VOLANT RICHARD P
IPC: H01L23/48 , H01L21/28 , H01L21/768
Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.
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公开(公告)号:DE112012004106T5
公开(公告)日:2014-07-10
申请号:DE112012004106
申请日:2012-08-03
Applicant: IBM
Inventor: COONEY EDWARD C , DUNN JAMES S , MARTIN DALE W , MUSANTE CHARLES F , RAINEY BETH-ANN , SHI LEATHEN , SPROGIS EDMUND J , TSANG CORNELIA K
Abstract: Verfahren zum Bonden von Substratoberflächen, gebondete Substratanordnungen sowie Entwurfsstrukturen für eine gebondete Substratanordnung. Es werden Einheiten-Strukturen (18, 19, 20, 21) eines Produkt-Chips (25) unter Verwendung einer ersten Oberfläche (15) eines Einheiten-Substrats (10) gebildet. Auf dem Produkt-Chip wird eine Verdrahtungsschicht (26) einer Zwischenverbindungsstruktur für die Einheiten-Strukturen gebildet. Die Verdrahtungsschicht wird planarisiert. Ein provisorischer Handhabungswafer (52) wird entfernbar an die planarisierte Verdrahtungsschicht gebondet. In Reaktion auf das entfernbare Bonden des provisorischen Handhabungswafers an die planarisierte erste Verdrahtungsschicht wird eine zweite Oberfläche (54) des Einheiten-Substrats, die entgegengesetzt zu der ersten Oberfläche ist, an ein endgültiges Handhabungssubstrat (56) gebondet. Anschließend wird der provisorische Handhabungswafer von der Anordnung entfernt.
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公开(公告)号:GB2509683B
公开(公告)日:2015-07-29
申请号:GB201408711
申请日:2012-08-03
Applicant: IBM
Inventor: COONEY EDWARD C , DUNN JAMES S , MARTIN DALE W , MUSANTE CHARLES F , RAINEY BETH-ANN , SHI LEATHEN , SPROGIS EDMUND J , TSANG CORNELIA K
IPC: H01L23/522 , H01L21/768 , H01L23/528
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公开(公告)号:CA2828498A1
公开(公告)日:2012-12-27
申请号:CA2828498
申请日:2012-06-19
Applicant: IBM
Inventor: ANDRY PAUL S , FAROOQ MUKTA G , HANNON ROBERT , IYER SUBRAMANIAN S , KINSER EMILY R , TSANG CORNELIA K , VOLANT RICHARD P
IPC: H01L21/28 , H01L21/768
Abstract: The present disclosure provides a thermo-mechanically reliable copper TSV and a technique to form such TSV during BEOL processing. The TSV constitutes an annular trench which extends through the semiconductor substrate. The substrate defines the inner and outer sidewalls of the trench, which sidewalls are separated by a distance within the range of 5 to 10 microns. A conductive path comprising copper or a copper alloy extends within said trench from an upper surface of said first dielectric layer through said substrate. The substrate thickness can be 60 microns or less. A dielectric layer having interconnect metallization conductively connected to the conductive path is formed directly over said annular trench.
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公开(公告)号:DE112012001870T5
公开(公告)日:2014-03-27
申请号:DE112012001870
申请日:2012-06-19
Applicant: IBM
Inventor: FAROOQ MUKTA G , HANNON ROBERT , VOLANT RICHARD P , ANDRY PAUL S , IYER SUBRAMANIAN S , KINSER EMILY R , TSANG CORNELIA K
IPC: H01L21/28 , H01L21/768
Abstract: Die vorliegende Offenbarung stellt einen thermo-mechanisch zuverlässigen Kupfer-TSV sowie eine Technik zum Bilden eines derartigen TSV während eines BEOL-Prozessablaufs bereit. Der TSV bildet einen ringförmigen Graben, der sich durch das Halbleitersubstrat hindurch erstreckt. Das Substrat definiert die inneren und äußeren Seitenwände des Grabens, wobei die Seitenwände durch einen Abstand innerhalb des Bereichs von 5 bis 10 Mikrometer separiert sind. Ein leitfähiger Pfad, der Kupfer oder eine Kupfer-Legierung aufweist, erstreckt sich innerhalb des Grabens von einer oberen Fläche der ersten dielektrischen Schicht durch das Substrat hindurch. Die Dicke des Substrats kann 60 Mikrometer oder weniger betragen. Direkt über dem ringförmigen Graben ist eine dielektrische Schicht mit einer Zwischenverbindungsmetallisierung ausgebildet, die mit dem leitfähigen Pfad leitfähig verbunden ist.
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