公开(公告)号：JPH10333985A

公开(公告)日：1998-12-18

申请号：JP9183998

申请日：1998-04-03

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  DODSON JOHN STEVEN ,  KAISER JOHN MICHAEL ,  JERRY DON LEWIS

IPC: G06F15/16 ,  G06F12/08 ,  G06F15/177 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To permit an efficient intervention of data in a shared state by making the intervention possible as an additional processing when two or more caches keep related data in shared state. SOLUTION: A cache coherency protocol is provided with the five states of latest reference R, modification M, exclusion E, sharing S and invalidation I. Then, a processor for accessing a data value detects the transfer of display and the data are supplied from the cache provided with the copy of the latest reference R. The cache provided with the copy of the latest reference R changes the display and turns it to the display of sharing S at the time of supplying the data and the processor which accesses the data is turned to the display of the latest reference R thereafter. Also, in the case that the processor intends to write the data value, the cache provided with the copy of the latest reference R first is turned to the display of the invalidation I. Thus, by supplying the intervention to the shared data, memory waiting time is largely improved.

公开(公告)号：JPH10320282A

公开(公告)日：1998-12-04

申请号：JP9610198

申请日：1998-04-08

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  DODSON JOHN STEVEN ,  JERRY DON LEWIS

IPC: G06F11/34 ,  G06F12/08

Abstract: PROBLEM TO BE SOLVED: To provide a method and a system for managing a cache in a data processing system. SOLUTION: The data processing system including a communication network connecting plural devices is provided. A 1st device out of plural ones includes plural requesters (or queues) and one corresponding inherent tag out of plural inherent tags is permanently allocated to each requester. In response to a communication request by a requester in the 1st device, the tag allocated to the requester is transferred to the communication network together with a requested communication transaction. The data processing system includes a cache having a cache directory 60. A status index indicating the status of at least one of plural data entries of the cache is stored in the directory 60. In response to the reception of a cache operation request, whether the status index is to be updated or not is checked.

公开(公告)号：JPH10307748A

公开(公告)日：1998-11-17

申请号：JP9342298

申请日：1998-04-06

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  JOHN STEPHEN DODSON ,  JERRY DON LEWIS ,  DEREK EDWARD WILLIAMS

IPC: G06F12/00 ,  G06F13/364

Abstract: PROBLEM TO BE SOLVED: To obtain the improved method and system for controlling access to the common resource by allocating a current priority level which is decided at random as to a previous priority level of a requester and allowing a request for access to the resource in response to the current priority level of the requester. SOLUTION: The number of requests for access to the common resource which can be allowed at the same time is less than the number of requests that requesters 12, 14, 16 and 18 can generate. A resource controller 20, therefore, allows only a requester selected out of the requesters 12, 14, 16 and 18 according to the priority levels to make a request when receiving requests for access to the common resource 22 more than the number of requests that can be allowed at the same time. At this time, the resource controller 20 allocates the at least top priority to one of the requesters 12, 14, 16 and 18 on a substantially on-deterministic basis by making use of input from a pseudo- random number generator 24.

公开(公告)号：JPH10301849A

公开(公告)日：1998-11-13

申请号：JP9745798

申请日：1998-04-09

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  JOHN STEPHEN DODDSON ,  JERRY DON LEWIS

IPC: G06F12/08

Abstract: PROBLEM TO BE SOLVED: To correctly track a sector valid at the level of a higher order without executing a useless bus operation by displaying that the sector of a cache line inside a second cache is changed upstream by the cache of a second level. SOLUTION: Three 'U' states are provided so as to indicate which sector inside the cache line is changed, or whether enable cache write through operation is executed to the cache line. Then, a first value is loaded into a cache line block inside the cache of the first level of a processor and the sector of the cache line inside the cache of the second level. Then, the value inside the cache line block inside the cache of the first level is changed. Then, it is displayed by the cache of the second level that the cache line inside the cache of the second level is changed upstream.

公开(公告)号：JPH10289156A

公开(公告)日：1998-10-27

申请号：JP7872198

申请日：1998-03-26

Applicant: IBM

Inventor： RAVI KUMER ARIMIRI ,  JOHN STEPHEN DODDSON ,  KAISER JOHN MICHAEL ,  JERRY DON LEWIS

IPC: G06F15/16 ,  G06F12/08 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To improve the memory waiting time related to a reading type operation by making a requester processor issue a message to try to read an unchanged copy of the value that is latest read and then making a specific cache transfer an answer to show that it can supply the value. SOLUTION: The value are loaded to plural caches from the addresses of a memory device, and a specific cache including an unchanged copy of the value that is latest read is identified among those caches and marked. At the same time, other caches including the unchanged sharing copies are also copied. Then a requester processor issues a message to try to read those value from the addresses of the memory device, and the specific cache transfers an answer to show that it can supply these value. Under such conditions, a protocol including the R which designates a block that is latest read is used in addition to the changing, exclusive, shared and invalid states in order to confirm the cache that owns the unchanged value.

公开(公告)号：JPH10307756A

公开(公告)日：1998-11-17

申请号：JP7887398

申请日：1998-03-26

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  LEO JAMES CLARK ,  JOHN STEPHEN DODDSON ,  JERRY DON LEWIS

IPC: G06F12/08 ,  G06F12/12

Abstract: PROBLEM TO BE SOLVED: To obtain an improved cache for the processor in a computer system by introducing randomness of certain level selectively in substitution algorithm and excluding a cache block according to the substitution algorithm. SOLUTION: The cache 60 includes a cache entry array 62 having various values, a cache directory 64 for tracing entries, and a substitution controller 66 which uses LRU algorithm altered selectively with a random number. Then when slight randomness is desirable, small randomness is introduced in a 2nd deformation example 70 and the substitution algorithm is altered. In a final modification example 74, no LRU bit is used and a block excluded in an 8- member class is completely selected with three random bits. Therefore, this is applicable to a single-processor computer system and a multiprocessor computer system.

公开(公告)号：JPH10301907A

公开(公告)日：1998-11-13

申请号：JP9777198

申请日：1998-04-09

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  JOHN STEPHEN DODDSON ,  JERRY DON LEWIS ,  DEREK EDWARD WILLIAMS

IPC: G06F15/16 ,  G06F13/364 ,  G06F15/177

Abstract: PROBLEM TO BE SOLVED: To minimize waiting time and to suppress live lock by allocating highest present priority among plural present priorities to the priority before plural requesters at random and approving a selected request in response to access to the shared resources of the plural requesters. SOLUTION: A resource controller 20 controls the access by the requesters 12-18 to the shared resource 22. In this case, a performance monitor 54 monitors and counts selected events inside a data processing system 10 including the request from the requesters 12-18. Then, at the time of receiving the requests more than the access to the shared resource 22 simultaneously approvable by the resource controller 20, the resource controller 20 utilizes input from a pseudo random generator 24, allocates the highest priority to one of the requesters 12-18 by a practically non-critical method and approves the request of only the selected one of the requesters 12-18 corresponding to the priority.

公开(公告)号：JPH10301851A

公开(公告)日：1998-11-13

申请号：JP9600798

申请日：1998-04-08

Applicant: IBM

Inventor： RAVI KUMAR ARIMIRI ,  JOHN STEPHEN DODDSON ,  JERRY DON LEWIS

IPC: G06F12/08 ,  G06F9/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/42

Abstract: PROBLEM TO BE SOLVED: To provide improved method and system for sharing cache memory data by reading requested data from a cache memory inside a processor before composite responses are returned from all the processors inside a data processing system to the processor. SOLUTION: The data processing system is provided with at least one CPU 11a-11n and provided with at least one each of primary cache 12a 12n and secondary cache 13a-13n and one high performance I/O device 16a-16n. In response to the request of the data by the high performance I/O device 16a-16n inside the data processing system, an intervention response is issued from the CPU 11a-11n provided with the requested data inside the data processing system. Then, the requested data are read from the secondary cache 13a-13n inside the CPU 11a-11n before the composite response is returned from all the CPUs 11a-11n inside the data processing system to the CPU 11a-11n.

公开(公告)号：JPH10289155A

公开(公告)日：1998-10-27

申请号：JP7870898

申请日：1998-03-26

Applicant: IBM

Inventor： RAVI KUMER ARIMIRI ,  JOHN STEPHEN DODDSON ,  KAISER JOHN MICHAEL ,  JERRY DON LEWIS

IPC: G06F15/16 ,  G06F12/08 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To improve the memory waiting time related to a reading type operation by making a requester processor issue the messages to try to read the unchanged sharing copies of value of the 1st and 2nd caches and then making one of caches transfer an answer to show that it can supply those cache value. SOLUTION: The value are loaded to at least 1st and 2nd caches from the addresses of a memory device, and the marks are added to both caches to show that they include the unchanged sharing copies of the value. Then a requester processor issues a message to show to try to read these value from the addresses of the memory device, and one of both caches transfers an answer to show that it can supply the value. Under such conditions, a protocol including the R which designates a block that is latest referred to is used in addition to the changing, exclusive, shared and invalid states in order to confirm the cache that owns the unchanged value.

公开(公告)号：JPH10289154A

公开(公告)日：1998-10-27

申请号：JP7869098

申请日：1998-03-26

Applicant: IBM

Inventor： RAVI KUMER ARIMIRI ,  JOHN STEPHEN DODDSON ,  KAISER JOHN MICHAEL ,  JERRY DON LEWIS

IPC: G06F15/16 ,  G06F12/08 ,  G06F15/163

Abstract: PROBLEM TO BE SOLVED: To improve the memory waiting time caused by a reading type operation by making a requester processor issue a message to try to read an unchanged copy of the value that is exclusively held in a cache and them making the cache transfer an answer to show that it can supply the value. SOLUTION: The value is loaded from an address of a memory device to the 1st one of plural caches which are related to the processors of a computer system, and a mark is added to the cache to show that it includes an unchanged copy of the value held exclusively. Then a requester processor issues a message to show to try to read the value from an address of a memory device, and the 1st cache transfers an answer to show that it can supply the value. Under such conditions, a protocol including the R which designates a block that is latest referred to is used in addition to the changing, exclusive, shared and invalid states in order to confirm the cache that owns the unchanged value.