公开(公告)号：CA2130978C

公开(公告)日：1997-09-30

申请号：CA2130978

申请日：1994-08-26

Applicant: IBM

Inventor： KENNEY DONALD M ,  BRONNER GARY B ,  DEBROSSE JOHN K

IPC: H01L21/76 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: A deep trench type DRAM cell with shallow trench isolation has a buried polysilicon strap that is defined without the use of a separate mask by depositing the strap material over at least the deep trench before shallow trench definition and using the shallow trench isolation mask to overlap partially the deep trench, thereby defining the strap during the process of cutting the shallow trench.

公开(公告)号：DE69019414D1

公开(公告)日：1995-06-22

申请号：DE69019414

申请日：1990-02-13

Applicant: IBM

Inventor： KENNEY DONALD M

IPC: H01L27/10 ,  H01L21/8242 ,  H01L27/108

Abstract: A very small memory cell utilizing only two squares at a major surface is provided which includes a semiconductor substrate (26) having a major surface and a trench (24) disposed therein having a longitudinal axis, a storage capacitor (16) having a storage node (20) disposed within a given sidewall of the trench (24), a switching device (12) coupled to the storage capacitor (16) and having an elongated current carrying element (22) disposed within the given sidewall with its longitudinal direction arranged parallel to that of the longitudinal axis of the trench (24) and a control element (14) disposed on the sidewall of the trench (24) between the storage capacitor (16) and the elongated current carrying element (22), and an electrically conductive line (28) disposed on the major surface of the semiconductor substrate (26) in a direction orthogonal to the longitudinal axis of the trench (24) and in contact with the control element (14) of the switching device (12). Furthermore, two complete memory cells (10A, 10B) are formed at each trench-word line intersection with one cell formed on each side of the trench (24) at each intersection.

公开(公告)号：CA1169557A

公开(公告)日：1984-06-19

申请号：CA378812

申请日：1981-06-02

Applicant: IBM

Inventor： KENNEY DONALD M

IPC: H01L27/10 ,  H01L21/306 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/74 ,  H01L29/749 ,  H01L29/78 ,  H01L21/308 ,  G11C11/34

Abstract: HIGH DENSITY V-MOS MEMORY ARRAY A method for providing high density dynamic memory cells which provides self-alignment of both V-MOSFET device elements and their interconnections through the use of a device-defining masking layer having a plurality of parallel thick and thin regions. Holes are etched in portions of the thin region with the use of an etch mask defining a plurality of parallel regions aligned perpendicular to the regions in the masking layer. V-MOSFET devices having selfaligned gate electrodes are formed in the holes and device interconnecting lines are formed under the remaining portions of the thin regions. A combination of anisotropic etching and directionally dependent etching, such as reaction ion etching, may be used to extend the depth of V-grooves. A method of eliminating the overhang of a masking layer after anisotropic etching includes the oxidation of the V-groove followed by etching to remove both the grown oxide and the overhang is also disclosed. BU-9-78-014

公开(公告)号：CA1159953A

公开(公告)日：1984-01-03

申请号：CA377171

申请日：1981-05-08

Applicant: IBM

Inventor： GARNACHE RICHARD R ,  KENNEY DONALD M ,  THOMA NANDOR G

IPC: H01L21/28 ,  H01L21/768 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L29/423 ,  H01L29/78

Abstract: V-MOS Device with Self-Aligned Multiple Electrodes High density VMOSFET devices, particularly single transistor memory cells, are provided by use of series of simplified self-aligning process steps. Gate electrodes, source/drain regions and source/ drain contacts are provided with the aid of an initial mask-less photoresist removal process in which a relatively thick layer of self-leveling photoresist is uniformly removed in order to define portions of a gate electrode within the recess of a V-groove. The gate electrode subsequently acts as a self-aligned mask to define implanted source/ drain regions also within the V-groove and to enable second level interconnecting metallurgy contacts to be formed along the sidewalls of the V-groove. BU-978013

公开(公告)号：CA2051566A1

公开(公告)日：1992-04-25

申请号：CA2051566

申请日：1991-09-17

Applicant: IBM

Inventor： DOBUZINSKY DAIVD M ,  HARMON DAVID L ,  KASI SRINANDAN R ,  KENNEY DONALD M ,  NGUYEN SON V ,  NGUYEN TUE ,  PAN PAI-HUNG

IPC: C23C8/36 ,  H01L21/31 ,  H01L21/316 ,  H01L21/321 ,  H01L21/8242 ,  H01L27/108 ,  C23C4/02 ,  C23C4/04 ,  H01L21/76

Abstract: U9-90-033 A process for forming a thin film on a surface of a semiconductor device. The process involves formation of a silicon dioxide film by plasma enhanced thermal oxidation, employing a mixture of ozone and oxygen which are generated separately from the reactor chamber in a volume ratio of about 1-10/1, preferably about 5-7/1, at a temperature generally below 440.degree.C, preferably about 350-400.degree.C. The process is used to form sidewall oxide spacers on polysilicon gates for field effect transistors. A relatively fast oxidation rate is achieved at a temperature significantly below that employed in conventional oxidation processes, and this serves to reduce dopant diffusion from the polysilicon. In addition, the resulting film demonstrates low stress with good conformal step coverage of the polysilicon gates. Another use of the process is to grow thin gate oxides and oxide-nitride-oxide with a thickness of less than 100 .ANG.. An oxide film of uniform thickness is formed by controlling the temperature, RF power, exposure time and oxygen/ozone ratio for thin gate oxide (

公开(公告)号：CA1289243C

公开(公告)日：1991-09-17

申请号：CA549648

申请日：1987-10-19

Applicant: IBM

Inventor： KENNEY DONALD M

IPC: H01L27/04 ,  H01L21/285 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

Abstract: A one-device shared trench memory cell, in which the polysilicon and dielectric layers within the trench extend above the surface of the trench to form a mandrel structure. A layer of polysilicon is conformably deposited on the mandrel structure. Dopant ions are diffused from the doped polysilicon within the trench to the conformal polysilicon layer, and from the conformal polysilicon layer, and from the conformal polysilicon layer to a portion of the substrate disposed thereunder. The conformal polysilicon is etched in a solvent that preferentially attacks undoped polysilicon, to provide and is a bridge contact that is self-aligned to the polysilicon within the trench and to the diffusion region. A plurality of FETs formed on either side of the trench, by use of a sidewall-defined gate electrode to maximize density. The cell produces a "poly-to-poly" and "poly-to-substrate" storage capacitor combination that maximizes charge storage capability.

公开(公告)号：CA1248231A

公开(公告)日：1989-01-03

申请号：CA517130

申请日：1986-08-28

Applicant: IBM

Inventor： KENNEY DONALD M

IPC: H01L27/10 ,  G11C11/34 ,  H01L21/762 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108

Abstract: High Density Memory A memory cell formed in a groove or trench in a semiconductor substrate is provided which includes a storage capacitor located at the bottom and along the lower portion of the sidewalls of the trench, a bit/sense line disposed at the surface of the semiconductor substrate adjacent to the trench, a transfer device or transistor located on the sidewall of the trench between the capacitor and the bit/sense line and a field shield for electrically isolating the storage capacitor from an adjacent cell formed in the same semiconductor substrate.

公开(公告)号：CA1166761A

公开(公告)日：1984-05-01

申请号：CA362828

申请日：1980-10-20

Applicant: IBM

Inventor： GARNACHE RICHARD R ,  KENNEY DONALD M

IPC: H01L21/28 ,  H01L21/306 ,  H01L21/336

Abstract: METHOD FOR PROVIDING SELF-ALIGNED: CONDUCTOR IN A V GROOVE DEVICE A method for providing self-aligned conductors in vertically integrated semiconductor devices which includes providing recesses in the surface of a semiconductor substrate for the fabrication of Vgroove devices, providing a conductive layer over the surface and then applying a layer of masking material over the conductive layer to form a planar upper surface, selectively etching the masking material until it remains only in the recesses and then selectively etching the exposed portion of the conductive layer. BU-9-78-012

公开(公告)号：CA980665A

公开(公告)日：1975-12-30

申请号：CA166915

申请日：1973-03-13

Applicant: IBM

Inventor： FITZGIBBONS WILLIAM A ,  MICHAUD RONALD A ,  KENNEY DONALD M

IPC: C30B31/02 ,  H01L21/22 ,  H01L21/225 ,  H01L21/306

Abstract: 1397684 Diffusion in semi-conductors INTERNATIONAL BUSINESS MACHINES CORP 8 March 1973 [6 April 1972] 11389/73 Heading H1K In a semi-conductor diffusion process an oxide layer containing the dopant is first vapour deposited on the semi-conductor body under conditions such that a dopant-rich interface layer of a material containing both the semiconductor and the dopant forms beneath the oxide layer and an initial concentration of the dopant enters a shallow layer of the semiconductor beneath the interface layer. The atmosphere around the body is then altered to an oxidizing state, the other conditions preferably remaining unchanged, so that the interface layer is converted to a soluble oxide which is subsequently removed by etching together with the dopant-containing oxide layer thereon. A drive-in diffusion is then carried out, preferably in an oxidizing atmosphere, to redistribute the initial dopant concentration from the shallow layer. For a Si body with B as the dopant the dopant-containing oxide is B 2 O 3 deposited, in an aperture in an oxide mask, from a vapour whose source is boron nitride slices having their outer surfaces oxidized to form B 2 O 3 . An inert carrier gas such as nitrogen is used. The Si body is maintained at 800-1300‹ C. during the oxide deposition process. The interface layer formed in these conditions is believed to be SiB 6 , which converts to a soluble borosilicate glass on the addition of oxygen and/or steam to the atmosphere. As, as a dopant, and Ge, as a semiconductor material, are also mentioned.