公开(公告)号：CA830032A

公开(公告)日：1969-12-16

申请号：CA830032D

Applicant: IBM

Inventor： KNAUFT GUENTER ,  SPRUTH WILHELM ,  SCHONBUCH WEIL I ,  BERGMANN KURT ,  LAMPARTER HELMUT ,  ROTHAUSER ERNST

公开(公告)号：CA754739A

公开(公告)日：1967-03-14

申请号：CA754739D

Applicant: IBM

Inventor： LAMPARTER HELMUT ,  KNAUFT GUENTER ,  SPRUTH WILHELM

公开(公告)号：IT1162778B

公开(公告)日：1987-04-01

申请号：IT2585079

申请日：1979-09-20

Applicant: IBM

Inventor： HAJDU JOHANN ,  KNAUFT GUENTER

IPC: G01R31/28 ,  G01R31/3185 ,  G01T7/00 ,  G06F11/26 ,  G11C29/00 ,  H01L21/66 ,  H01L21/822 ,  H01L27/04 ,  G11C

Abstract: An LSI integrated semiconductor circuit system comprised of a plurality of interconnected minimum replaceable units. The system and each minimum replaceable unit fully conforms to the Level Sensitive Scan Design (LSSD) Rules. [Level Sensitive Scan Design Rules are fully disclosed and defined in each of the following U.S. Pat. Nos. 3,783,254, 3,761,695, 3,784,907 and in the publication "A Logic Design Structure For LSI Testability" by E. B. Eichelberger and T. W. Williams, 14th Design Automation Conference Proceedings, IEEE Computer Society, June 20-22, 1977, pages 462-467, New Orleans, La.]. Each of the minimum replaceable units includes a shift register segment having more than two shift register stages. Each register stage of each shift register segment of each minimum replaceable unit includes a master flip-flop (latch) and a slave flip-flop (latch). Connection means is provided for connecting the shift register segments of said minimum replaceable units into a single shift register. Additional controllable circuit means including test combinational circuit means is provided for setting a predetermined pattern in only said first two stages of each shift register segment of said minimum replaceable units. The additional circuit means facilitates and is utilized in testing the circuit integrity (stuck faults and continuity) of each minimum replaceable unit.

公开(公告)号：DE1941638A1

公开(公告)日：1971-02-18

申请号：DE1941638

申请日：1969-08-16

Applicant: IBM DEUTSCHLAND

Inventor： EBBINGHAUS KURT DR-ING ,  VON DIPL-ING KROGH CHRISTOPH ,  VOGT EDWIN DR-ING ,  KNAUFT GUENTER

IPC: G06F9/32 ,  G06F9/10

公开(公告)号：DE1935258A1

公开(公告)日：1971-01-14

申请号：DE1935258

申请日：1969-07-11

Applicant: IBM DEUTSCHLAND

Inventor： HAJDU JOHANN ,  KNAUFT GUENTER ,  REICHL LEOPOLD ,  EDWIN VOGT DIPL-ING DR ,  PAINKE HELMUT

IPC: G06F9/46 ,  G06F9/48

公开(公告)号：DE1927549A1

公开(公告)日：1970-12-03

申请号：DE1927549

申请日：1969-05-30

Applicant: IBM DEUTSCHLAND

Inventor： KNAUFT GUENTER ,  LEOPOLD REICHL DIPL-ING ,  EDWIN VOGT DIPL-ING ,  KOEDERITZ FRITZ ,  PAINKE HELMUT ,  WEBER HERMANN ,  HERMANN LAMPE HANS ,  KACHENAUER ROBERT

IPC: G06F11/22 ,  G06F11/267 ,  G06F11/273 ,  G06F13/00 ,  G06F13/42 ,  G06F3/02

Abstract: This disclosure is for a rearrangement of the input/output controls of a small central processing unit (CPU) to enable interspersed use of the input/output devices by the CPU and by the customer engineer. This configuration allows the engineer to read the status of the devices and to test their functions without interference with the CPU usage of the devices and without shutting down of the system.

公开(公告)号：DE1472003A1

公开(公告)日：1969-10-09

申请号：DE1472003

申请日：1965-05-24

Applicant: IBM

Inventor： HELMUT LAMPARTER DIPL-ING ,  KNAUFT GUENTER ,  WILHELM SPRUTH DR-ING

IPC: G10L19/00 ,  G10L19/02 ,  G10L1/00

公开(公告)号：DE1258910B

公开(公告)日：1968-01-18

申请号：DEJ0028205

申请日：1965-05-24

Applicant: IBM

Inventor： LAMPARTER DIPL-ING HELMUT ,  KNAUFT GUENTER ,  SPRUTH DR-ING WILHELM

IPC: G10L13/04 ,  G10L19/08 ,  G10L25/93 ,  G10L1/00

公开(公告)号：CA735084A

公开(公告)日：1966-05-24

申请号：CA735084D

Applicant: IBM

Inventor： LAMPARTER HELMUT ,  SPRUTH WILHELM ,  KNAUFT GUENTER

公开(公告)号：DE69123725T2

公开(公告)日：1997-06-12

申请号：DE69123725

申请日：1991-04-30

Applicant: IBM

Inventor： WEISS ULRICH ,  KNAUFT GUENTER ,  SCHMUNKAMP DIETMAR DIPL ING ,  LEPPLA BERND DIPL ING

IPC: H03K5/15

Abstract: An electrical circuit is described for generating clock pulses for a multi-chip computersystem which contains a clock generation chip and various logic circuit chips. The clock pulses used on the logic circuit chips are generated on the clock generation chip and are transferred to the logic circuit chips. For the generation of the clock pulses a so-called clocksplitter circuit is provided on the clock generation circuit. This clocksplitter generates two pulse strings out of a third pulse string which is derived from an oscillator. The clocksplitter contains a number of gates and latches which have an impact on the throughput time of a pulse to run through the clocksplitter, as well as on the skew of the two generated pulse strings. The invention provides an electrical circuit which has an improved throughput time and skew of the generated pulse strings.