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    Method and apparatus for checking a data transfer operation
    1.
    发明授权
    Method and apparatus for checking a data transfer operation 失效
    检查数据传输操作的方法和装置

    公开(公告)号：US3579185A

    公开(公告)日：1971-05-18

    申请号：US3579185D

    申请日：1968-09-20

    Applicant: IBM

    Inventor： SPRUTH WILHELM

    IPC: G06F11/10 ,  H04L1/00 ,  H04L1/10

    CPC classification number: G06F11/10 ,  H04L1/0045 ,  H04L1/0063

    Abstract: The accuracy of a data transfer operation, particularly one which involves loading a micro program into an alterable control storage device for use in a data processing system, is verified by deriving a check number from the transferred data and comparing the desired check number with a predetermined check number known to be correct. A variety of concepts may be used to obtain the derived check number such as successive logical Exclusive OR operations on transferred blocks of data or selected portions of the blocks.

    Data Processing Apparatus
    3.
    发明专利
    Data Processing Apparatus 未知

    公开(公告)号：GB1188433A

    公开(公告)日：1970-04-15

    申请号：GB4316168

    申请日：1968-09-11

    Applicant: IBM

    Inventor： SPRUTH WILHELM

    IPC: G06F9/22 ,  G06F11/08

    Abstract: 1,188,433. Error checking in data processors. INTERNATIONAL BUSINESS MACHINES CORP. 11 Sept., 1968 [27 Sept., 1967], No. 43161/68. Heading G4A. In data processing apparatus, a check number is generated for a series of groups of N data bits (e.g. micro-programme instructions or parts thereof) being transferred from one location (e.g. card reader) to another (e.g. core memory), by using N counting devices each counting the 0-to-1 and 1-to-0 changes in a respective bit position when the counting device is conditioned (see below), and the check number is compared with a stored check number to determine whether the transfer is complete or correct. The counting is modulo-2, each counting device being an EXCL-OR fed by the counting device input and the 1 output of a flip-flop, the EXCL-OR feeding the flip-flop, which provides the counting device output. In one embodiment, all the counting devices are conditioned for every group of bits, and three stored check numbers are provided any one of which or all in turn (manual or automatic selection) can be compared with the generated check number e.g. to determine if the micro-programme entered into the machine is applicable to this machine. In a modification, the counting devices are enabled in turn by a decoded clock-driven binary counter so that each counting device responds to a respective 1/Nth of the bit-groups. A further modification has 3 such binary counters forming a single binary counter and controlling respective check number generators each as above, each bit-group going to the three generators in common. In this case the 3 generated check numbers are compared with respective thirds of a stored check number.

    Improvements in vocoders
    5.
    发明专利
    Improvements in vocoders 未知

    公开(公告)号：GB1087305A

    公开(公告)日：1967-10-18

    申请号：GB2131465

    申请日：1965-05-20

    Applicant: IBM

    Inventor： LAMPARTER HELMUT ,  KNAUFT GUNTHER ,  SPRUTH WILHELM

    IPC: G10L19/00 ,  G10L19/02 ,  G10L19/04 ,  G10L25/93 ,  H03K21/00 ,  H04J3/17

    Abstract: 1,087,305. Vocoders. INTERNATIONAL BUSINESS MACHINES CORPORATION. May 20, 1965 [May 26, 1964], No. 21314/65. Heading H4R. In an analysis synthesis telephone system an excitation function is derived comprising a pulse sequence of a repetition frequency equal to the fundamental frequency of the speech input, which pulse sequence is used to control the sampling of the energy in the spectrum analysis bands. During unvoiced sounds, when the speech input is of such a character as to prevent the production of a satisfactory excitation function, an auxiliary pulse generator is switched in to control the sampling in the spectrum analysis bands. Fig. 3 shows an analyser in which a speech signal at 1 is applied to a low pass filter 2 and a zero crossing detector 3 to generate a train of pulses at the fundamental frequency of the speech input. These pulses are fed via an OR gate 17 to a sampling pulse generator 14 to generate pulses to open gates 8 1 to 8 n to feed samples from the outputs of the band pass filters 7 1 to 7 n , arranged to divide the frequency spectrum of the incoming speech into a number, n, of frequency bands, to the analog to digital converters 9 1 to 9 n , the outputs of which define the energy distribution across the frequency spectrum of the speech, i.e. the aggregate function. If the speech input is such that the zero crossing detector fails to produce pulses a single shot circuit, which is maintained in its metastable state by the pulses from the zero crossing detector, reverts to its stable state in 12 m. sees. to cause the pulse generator 16 to supply pulses, via OR gate 17, to the sampling generator 14 at 3 m. sec. intervals until pulses reappear at the output of the zero crossing detector. The pulse output from the zero crossing detector 3 is also applied to an " AND " gate 6 to feed the count of counter 5 to the output circuit 19, the counter being subsequently reset by the same pulse so that the counter output is a measure of the interval between pulses, the count being transmitted as the excitation function. The speech input at 1, via an amplifier 10 and level detector 11, keeps a single shot 12 in its metastable state to maintain gate 13 open so that if the speech level remains at zero for longer than 100 m. sees. the single shot 12 reverts to its stable state to inhibit the feed of sampling pulses from generator 14 to the gates 91 to 9 n . Voiced/unvoiced detector 18 described in detail with reference to Fig. 4 (not shown) comprises a logic circuit which produces an output, either when all the outputs of a number of the lowest frequency analysis filters are zero, or when the outputs of these filters is lower than that of groups of the same number of higher frequency analysis filters. Synthesiser circuit, Fig. 5.-Excitation function signals from the input-distributer circuit 26 are fed to a register 27 which sets counter 28 in accordance with the count corresponding to the interval between the excitation function pulses. The counter then counts, under the control of generator 29, down to zero when it generates a pulse to feed to distributer 35 via OR gate 36 before being reset in accordance with the following count in register 27. Meanwhile the aggregate function signals and voiced/ unvoiced signals are fed to the register 30, the voiced/unvoiced signals being used via a trigger circuit 37 to enable gate 38 to feed pulses from the auxiliary generator 39 to OR gate 36. and hence the distributer 35, in the absence of pulses from the counter 28 during unvoiced sounds. The digital to analog converter 31 converts the received aggregate function signals to analogue signals whose amplitudes vary according to the spectral energy distribution of the original speech, these signals being fed to the gates 32 1 to 32 n where they are gated appropriately by the pulses from the distributer 35. The resulting signals are passed through band-pass filters similar to the analysis filters in the analyser to an adding circuit 34 from which the synthesised speech is obtained. Since the mean frequency of the auxiliary generator 39, about 1000 c./s., is much higher than the fundamental speech frequency from counter 28, about 80 to 300 c./s., during unvoiced sounds the sample pulses from the digital to analog converter are narrowed in order that the energy intensity of the synthesised unvoiced sounds is made commensurate with that of the voiced sounds.

    DATA STORAGE SYSTEM
    9.
    发明专利
    DATA STORAGE SYSTEM 未知

    公开(公告)号：GB1248273A

    公开(公告)日：1971-09-29

    申请号：GB1665669

    申请日：1969-03-31

    Applicant: IBM

    Inventor： LOUIS HELMUT PETER ,  SCHUENEMANN CLAUS HEINRICH ,  SPRUTH WILHELM

    IPC: G11C11/41 ,  G11C11/36 ,  G11C11/39 ,  G11C11/411 ,  H03K3/012 ,  H03K3/35

    Abstract: 1,248,273. Data storage. INTERNATIONAL BUSINESS MACHINES CORP. 31 March, 1969 [30 March, 1968], No. 16656/69. Heading G4C. During read or write operations in a data store, a relatively high power voltage is supplied to the addressed storage elements and the voltage supply to each unaddressed element is interrupted, whereas at other times a relatively low standby voltage is supplied to all the elements. In the matrix thyristor or SCR store of Fig. 1, the voltages referred to are applied between row and column leads X, Y. Row leads B0, B1 are used for bits to be written or being non-destructively sensed. A second embodiment uses single-emitter thyristors, leads X being dispensed with, their function being taken over by the bit leads, B0, B1. Power consumption in the matrix is the same during and between read and write operations. Monolithic construction is mentioned.

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