公开(公告)号：CA981365A

公开(公告)日：1976-01-06

申请号：CA163470

申请日：1973-02-08

Applicant: IBM

Inventor： DAVIDSON EVAN E ,  LANE RALPH D ,  SAIA JERRY

IPC: G11C11/419 ,  G11C11/404 ,  G11C11/409 ,  G11C11/4091 ,  H03K5/02

Abstract: 1367058 Capacitive memory cells INTERNATIONAL BUSINESS MACHINES CORP 1 Feb 1973 [20 March 1972] 5028/73 Heading H3T A capacitor data storage cell CS is refreshed during a read operation by a latch circuit 9. Data is read from CS by a F.E.T. Q1 in response to a low voltage on the word line 4. If a high level (1) is stored, a transistor 7 conducts to raise the bit line 5, and this triggers the latch 9 which is an SCR in Fig. 1. The latch acts to raise the voltage on line 5 above that which was necessary to initiate triggering, and this raised voltage is fed through another transistor 6 to refresh the storage cell CS. The capacitance of the line 5 is discharged by a transistor 12 which is turned on at the beginning of a read operation, but turned off before the word line 4 voltage is lowered to effect reading. Transistors 12 and Q1 are turned on together, however, if it is desired to write a "0" (i.e. CS is earthed). To write a "1" a further transistor 13 is turned on to raise bit line 5 to +V while word line 4 turns on Q1. Instead of the SCR 9, an emitter coupled pair (16, 17, Fig. 2, not shown) with a positive feedback emitter follower 20, may be used; this has to be reset by a transistor inverter 25. The collector load in the emitter coupled pair may be either a resistor, or (Fig. 3, not shown) a F.E.T. (31) with a gate-source capacitor which is precharged by a further F.E.T. 29 and which boosts conduction of the load F.E.T. (31). The load F.E.T. (31) is fed with a pulsed power supply which is high during a read (refresh) operation, but goes low thereafter and resets the latch by way of the feedback transistor (30).

公开(公告)号：DE2359153A1

公开(公告)日：1974-07-11

申请号：DE2359153

申请日：1973-11-28

Applicant: IBM

Inventor： HANSEN AAGE A ,  LANE RALPH D

IPC: G11C11/41 ,  G11C11/34 ,  G11C11/413 ,  G11C16/06 ,  G11C16/08 ,  G11C17/00 ,  G11C7/00

Abstract: A high-voltage integrated driver circuit for driving the word lines of a digital computer memory array of floating-gate avalanche-injection transistor memory cells, and for other applications where a high driving voltage is required. The disclosed driver circuit comprises a field-effect output transistor having a source electrode connected to a respective word line, a drain electrode adapted to have a chip select pulse signal applied thereto, and a gate electrode connected to selectably operable circuitry which may be conditioned either to a first state for clamping the voltage of the gate to cut off the output transistor and thereby maintain the output and the word line at a first voltage level, or to a second state for unclamping the voltage of the gate of the output transistor to permit the voltage of the output and the respective word line to swing with a high amplitude so as to cause the selected memory cell transistor to go into avalanche breakdown and thereby charge its floating gate so as to store a bit of information in the selected cell.