公开(公告)号：DE10116639A1

公开(公告)日：2001-10-25

申请号：DE10116639

申请日：2001-04-04

Applicant: IBM

Inventor： LEENSTRA JENS ,  PILLE JUERGEN ,  SAUTTER ROLF ,  WENDEL DIETER

IPC: G06F9/38 ,  G11C8/16 ,  G11C11/417

Abstract: The buffer memory (12) has 64 inputs that are accessed by a write decoder (22) with a control connection to a comparator (20) having four switching stages coupled to data input lines (14). This allows the number of input ports to be reduced.

公开(公告)号：DE10110578A1

公开(公告)日：2001-10-18

申请号：DE10110578

申请日：2001-03-06

Applicant: IBM

Inventor： LEENSTRA JENS ,  MUELLER ANTJE ,  PILLE JUERGEN ,  WENDEL DIETER

IPC: G06F13/18 ,  G06F13/26

Abstract: A storage device and a method for determining the entry with the highest priority in a buffer memory. The method is characterized by the steps of operating a plurality of priority subfilter circuits each of them covering a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority, and selecting the entry associated with the highest priority subgroup. The storage device is able to be allocated and deallocated repeatedly during processing program instructions in a computer system. The storage device is further characterized by an operator for operating a plurality of priority subfilter circuits. Each of priority subfilter circuits covers a disjunct subgroup of the total of entries and each selecting the entry with the highest subgroup priority. The storage device is still further characterized by a selector for selecting the entry associated with the highest priority subgroup.

公开(公告)号：DE10110576A1

公开(公告)日：2001-10-11

申请号：DE10110576

申请日：2001-03-06

Applicant: IBM

Inventor： HOFSTEE PETER ,  LEENSTRA JENS ,  TAST HANS-WERNER ,  WENDEL DIETER

IPC: G01R31/3185 ,  G06F11/26

Abstract: The present invention relates to improvements concerning logic and timing verification as the testability of a hardware circuit comprising embeddings of dynamic logic circuits in a static environment. The clocked macros comprising the dynamic logic circuit are bounded at both input and output by latches, keeping input and output signals to the clocked macro static. The static input signals are processed with wave formatting means in order to generate a wave form usable for an evaluation by the dynamic logic circuit, and the dynamic logic output signal is converted back to a static signal by a set/reset latch such that it can be latched by the clock signal of the static embedding circuit. Thus, the analysis methods for timing and logic simulation during chip design can be the same as those used for static logic and, in particular, the LSSD testing methods can be used.

公开(公告)号：DE19910451A1

公开(公告)日：1999-11-04

申请号：DE19910451

申请日：1999-03-10

Applicant: IBM

Inventor： DAO TRONG SON ,  LEBER PETRA ,  LEENSTRA JENS

IPC: G06F9/38 ,  G06F15/163

Abstract: The single chip multiprocessor has 2 symmetrical processors (101,102) and a common execution unit, utilized by each of the processors, with transfer of data from each of the processors to the common execution unit in successive clock cycles. An Independent claim for a manufacturing method for a multiprocessor is also included.