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    APPARATUS AND METHOD FOR PROVIDING METERED CAPACITY OF COMPUTER RESOURCES
    11.
    发明专利
    APPARATUS AND METHOD FOR PROVIDING METERED CAPACITY OF COMPUTER RESOURCES 未知

    公开(公告)号：CA2519221A1

    公开(公告)日：2004-10-14

    申请号：CA2519221

    申请日：2004-03-22

    Applicant: IBM

    Inventor： GRIMM RANDALL LANE ,  BIRKESTRAND DANIEL CHARLES ,  SCHARDT TERRY LYLE ,  LEWIS DAVID OTTO

    IPC: G06F9/40 ,  G06F9/50 ,  H04L12/14 ,  G06F17/60

    Abstract: An apparatus and method provides the capability of metering temporary capaci ty on demand in a computer system. A resource-time is specified, such as processor-days. The actual usage of the resource is monitored, and the customer is charged for only the actual usage of the resource. In this manne r a customer may purchase a specified resource-time, and is only charged for t he time that the resource is actually used. The preferred embodiments extend to metering temporary capacity on demand in a logically partitioned computer system. If a resource is shared, the actual usage of the resource is monitored, and the customer is only billed for actual usage that exceeds a predetermined non-zero threshold.

    12.
    发明专利
    未知

    公开(公告)号：MX150980A

    公开(公告)日：1984-09-03

    申请号：MX18558581

    申请日：1981-01-16

    Applicant: IBM

    Inventor： HEISE NYLES NORBERT ,  HOFFMAN ROY LOUIS ,  KISS ISTVAN STEVE ,  LEWIS DAVID OTTO ,  PERTZBORN JAMES JOHN ,  ROBINSON THOMAS-SCOTT

    IPC: G06F13/12 ,  G06F12/10 ,  G06F13/10 ,  G06F13/18 ,  H04B1/00

    Abstract: In virtual storage data processing apparatus including real main storage, 10 a virtual address translation unit VAT 15 and a common I/O control unit 110 serving plural I/O devices, 150 the virtual address translation unit includes a resolved address register for each I/O device, a pool of resolved address registers and control logic responsive to a device specific CPU I/O command for initiating chaines I/O data transfers to cause the VAT apparatus to translate a first virtual address to be used in the chained data transfer operation and load the translated (resolved) address the appropriate resolved address register and responsive to a command from the shared control unit indicating that one of the commanded I/O devices is ready for data transfer to become nonresponsive to further CPU I/O commands and cause the VAT to resolve a succession of virtual addresses for the data transfer and to load the resolved addresses into resolved address registers of the pool whereby a data transfer operation can commence using the resolved address in the register unique to the I/O device which is first ready for data transfer and thereafter continue with data transfers using resolved addresses from the registers shared by all of the I/O devices but captured for use by the I/O device first ready for data transfer. Upon the data transfers being completed for that I/O device, the VAT resolves a succession of virtual addresses and loads them into the shared registers for use during data transfers by the next ready I/O device in response to a command from the shared I/O control unit.

    VIRTUAL MEMORY DATA PROCESSING SYSTEM
    13.
    发明专利
    VIRTUAL MEMORY DATA PROCESSING SYSTEM 未知

    公开(公告)号：DE2965382D1

    公开(公告)日：1983-06-16

    申请号：DE2965382

    申请日：1979-09-24

    Applicant: IBM

    Inventor： LEWIS DAVID OTTO ,  REED JOHN WALTER

    IPC: G06F13/12 ,  G06F12/10 ,  G06F13/10 ,  G06F3/04

    Abstract: This invention relates to a virtual memory data processing system, and the specification describes such a system in which apparatus is provided for enabling I/O adapters (4) to use virtual addresses. After each I/0 data transfer, the main memory (5) address involved in the transfer is incremented. This address is maintained in I/O register associated with the I/O adapter (4) performing the transfer. If a page boundary is crossed in the process of incrementing, the channel (3) forms an I/O event indicating the page crossing and calling for translation of the incremented address. When the I/O adapter (4) involved in the page crossing attempts a further data transfer, the channel (3) disconnects the I/O adapter. The channel (3) holds the I/O adapter (4) disconnected until the page crosing denoted by the I/O event has been resolved by translating the incremented address and providing a new main memory address for continuing the data transfer. Because the disconnect is effected by ignoring the priority of the disconnected adapter when it requests service, other adapters of lower priority can be serviced by the channel during the disconnect. When completion of the address translation is signalled, the I/O adapter is no longer held disconnected.

    17.
    发明专利
    未知

    公开(公告)号：DE2460011A1

    公开(公告)日：1975-07-10

    申请号：DE2460011

    申请日：1974-12-19

    Applicant: IBM

    Inventor： LEWIS DAVID OTTO ,  MILLER THOMAS HOWARD ,  SCHMITT STEVEN ALOI

    IPC: G06F3/00 ,  G06F13/10 ,  G06F9/00

    Abstract: A computer system executes instructions for an I/O device not attached to the system. A quasi I/O attachment device is responsive to the commands for the unattached I/O device and generates an interrupt condition. The interrupt condition causes the command instructions for the unattached I/O device to be translated to command instructions for an I/O device connected to the computer system. The I/O device attached to the system performs the designated operation and generates associated I/O device status data. This associated I/O device status data is translated into I/O device status data for the unattached I/O device and thus permits a program for operating an unattached I/O device to operate instead an I/O device attached to the system which otherwise could not be operated by that program. A second embodiment performs the emulation of the unattached I/O device remotely of the central processing unit in the computer system.

    VIRTUAL STORAGE DATA PROCESSING APPARATUS INCLUDING I/O
    19.
    发明专利
    VIRTUAL STORAGE DATA PROCESSING APPARATUS INCLUDING I/O 未知

    公开(公告)号：DE3071860D1

    公开(公告)日：1987-01-22

    申请号：DE3071860

    申请日：1980-12-12

    Applicant: IBM

    Inventor： LEWIS DAVID OTTO ,  PERTZBORN JAMES JOHN ,  ROBINSON THOMAS SCOTT ,  HEISE NYLES NORBERT ,  HOFFMAN ROY LOUIS ,  KISS ISTVAN STEVE

    IPC: G06F13/12 ,  G06F12/10 ,  G06F13/10 ,  G06F13/18

    Abstract: In virtual storage data processing apparatus including real main storage, 10 a virtual address translation unit VAT 15 and a common I/O control unit 110 serving plural I/O devices, 150 the virtual address translation unit includes a resolved address register for each I/O device, a pool of resolved address registers and control logic responsive to a device specific CPU I/O command for initiating chaines I/O data transfers to cause the VAT apparatus to translate a first virtual address to be used in the chained data transfer operation and load the translated (resolved) address the appropriate resolved address register and responsive to a command from the shared control unit indicating that one of the commanded I/O devices is ready for data transfer to become nonresponsive to further CPU I/O commands and cause the VAT to resolve a succession of virtual addresses for the data transfer and to load the resolved addresses into resolved address registers of the pool whereby a data transfer operation can commence using the resolved address in the register unique to the I/O device which is first ready for data transfer and thereafter continue with data transfers using resolved addresses from the registers shared by all of the I/O devices but captured for use by the I/O device first ready for data transfer. Upon the data transfers being completed for that I/O device, the VAT resolves a succession of virtual addresses and loads them into the shared registers for use during data transfers by the next ready I/O device in response to a command from the shared I/O control unit.

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