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公开(公告)号：IT7926082D0
公开(公告)日：1979-09-28
申请号：IT2608279
申请日：1979-09-28
Applicant: IBM
Inventor： MITCHELL GLEN ROBERT , HOUDEK MERLE EDWARD
Abstract: The present invention discloses an apparatus for the efficient translation of virtual addresses to main storage addresses by means of a hash index table which contains main storage addresses. Hash generator apparatus is provided for generating a uniform distribution of hash index table entry addresses from a non-uniform distribution of virtual addresses in a data processing system, where the size of the hash index table is variable and is based on the size of main storage. A field of bits within the virtual address corresponding to the page identification bits are reversed in order and aligned with two groups of bits from a field of bits within the virtual address corresponding to object identification bits, and the three groups of bits are applied to an EXCLUSIVE-OR circuit. The alignment of the three groups of bits and the size of the hash index table entry addresses generated by the present invention are based on the size of the hash index table.
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公开(公告)号：DE3273912D1
公开(公告)日：1986-11-27
申请号：DE3273912
申请日：1982-03-09
Applicant: IBM
Inventor： HOFFMAN ROY LOUIS , HOUDEK MERLE EDWARD , LOEN LARRY WAYNE , SOLTIS FRANK GERALD
IPC: G06F9/46 , G06F9/48 , G06F15/16 , G06F15/177
Abstract: The task handling arrangement is provided in a multiprocessor system in which each processor (5) includes a task dispatcher and a signal dispatcher. The signal dispatcher runs in a processor whenever a task dispatching element (TDE) is put on the task dispatching queue (TDQ) as a result of the task running in the processor. The signal dispatcher examines the TDEs enqueued on the TDQ and determines if any task dispatcher should be invoked, i.e. if any processor is running a lower priority task a task switch should occur. If so, it signals the selected processor to invoke its task dispatcher. After completing the task switch, the selected processor must invoke its signal dispatcher to determine if the task it had been performing should now be performed on some other processor in the multiprocessor system.
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公开(公告)号：DE2962460D1
公开(公告)日：1982-05-19
申请号：DE2962460
申请日：1979-09-24
Applicant: IBM
Inventor： MITCHELL GLEN ROBERT , HOUDEK MERLE EDWARD
Abstract: The present invention discloses an apparatus for the efficient translation of virtual addresses to main storage addresses by means of a hash index table which contains main storage addresses. Hash generator apparatus is provided for generating a uniform distribution of hash index table entry addresses from a non-uniform distribution of virtual addresses in a data processing system, where the size of the hash index table is variable and is based on the size of main storage. A field of bits within the virtual address corresponding to the page identification bits are reversed in order and aligned with two groups of bits from a field of bits within the virtual address corresponding to object identification bits, and the three groups of bits are applied to an EXCLUSIVE-OR circuit. The alignment of the three groups of bits and the size of the hash index table entry addresses generated by the present invention are based on the size of the hash index table.
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公开(公告)号：IT1165346B
公开(公告)日：1987-04-22
申请号：IT2608279
申请日：1979-09-28
Applicant: IBM
Inventor： MITCHELL GLEN ROBERT , HOUDEK MERLE EDWARD
Abstract: The present invention discloses an apparatus for the efficient translation of virtual addresses to main storage addresses by means of a hash index table which contains main storage addresses. Hash generator apparatus is provided for generating a uniform distribution of hash index table entry addresses from a non-uniform distribution of virtual addresses in a data processing system, where the size of the hash index table is variable and is based on the size of main storage. A field of bits within the virtual address corresponding to the page identification bits are reversed in order and aligned with two groups of bits from a field of bits within the virtual address corresponding to object identification bits, and the three groups of bits are applied to an EXCLUSIVE-OR circuit. The alignment of the three groups of bits and the size of the hash index table entry addresses generated by the present invention are based on the size of the hash index table.
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公开(公告)号：IT1165345B
公开(公告)日：1987-04-22
申请号：IT2608079
申请日：1979-09-28
Applicant: IBM
Inventor： MITCHELL GLEN ROBERT , KEMPKE WILLIAM GEORGE , JONES EUGENE REESE , HOUDEK MERLE EDWARD , RANWEILER JAMES GREGORY
Abstract: Tagged pointer handling apparatus is provided for implementation in a computer system wherein a tag bit is provided for each word in main storage. This invention provides for the mixing of data and pointers within the same storage space, and provides a capability for checking and verifying the validity of the pointers without affecting the performance or operation of other instructions. Only the tag instructions can set the tag bits ON in main storage; all other instructions store data and set the corresponding tag bits OFF. Thus, if a pointer was modified inadvertently by one of these data handling instructions, the fact that the pointer is untagged is detected and the values in the pointer are treated as invalid when the pointer is used by the Load and Verify Tags instruction. Instructions to load, store, set, move, extract and insert tags are implemented by the tagged pointer handling apparatus. A Load and Verify Tags instruction checks the validity of the pointer and if valid, loads the pointer into a specified general purpose register. A Store and Set Tags instruction stores the value in a specified general purpose register into main storage and sets the associated tag bits ON. A Move and Set Tags instruction moves a word from one location in main storage to another or the same location in main storage and sets the associated tag bits ON. A Move Characters and Tags instruction moves a word and the associated tag bits from one storage location to another storage location. An Extract Tags instruction fetches each word from an operand in main storage, extracts the tag bits, compresses the tag bits to one tag bit per quadword, and stores the tag bits in main storage as data. An Insert Tags instruction fetches the tag bits stored in main storage as data, expands the tag bits to one tag bit per word, and inserts them on each associated word of an operand in main storage.
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Patent Agency Ranking
公开(公告)号：DE2262004A1
公开(公告)日：1973-07-12
申请号：DE2262004
申请日：1972-12-19
Applicant: IBM
Inventor： HANSON CHARLES CHRISTIAN , HO JOSEPH PING LIONG , HOUDEK MERLE EDWARD
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公开(公告)号：DE3854037D1
公开(公告)日：1995-07-27
申请号：DE3854037
申请日：1988-09-27
Applicant: IBM
Inventor： HOUDEK MERLE EDWARD , LEWIS DAVID OTTO
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公开(公告)号：DE3485034D1
公开(公告)日：1991-10-17
申请号：DE3485034
申请日：1984-01-17
Applicant: IBM
Inventor： DANG LAM QUANG , GEER CHARLES PORTER , HOUDEK MERLE EDWARD , JONES REESE , SOLTIS GERALD , SOYRING JOHN ARTHUR , WALKER THOMAS MILTON
Abstract: Apparatus for compressing and buffering large amounts of data, transferring the buffered data to a slower speed storage device and controlling the stopping and starting of the central processing unit CPU (10) is provided for a virtual storage computer system where the data is collected in real time; the data being collected are all storage addresses to facilitate address tracing. Each real main storage address is collected at the external interface between the CPU (10) and main storage (50) and converted to a virtual address. The virtual address is compressed and entered into a large buffer (500) via buffer control logic (400). The buffer control logic sends a signal (441) to stop the CPU when the buffer becomes full and a signal (442) to restart it at the exact point it had stopped after the buffer (500) has been emptied by the transfer of data from it to a slower speed storage device.
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公开(公告)号：DE3480129D1
公开(公告)日：1989-11-16
申请号：DE3480129
申请日：1984-02-20
Applicant: IBM
Inventor： HOFFMAN ROY LOUIS , HOUDEK MERLE EDWARD , SOLTIS FRANK GERALD
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公开(公告)号：DE2961891D1
公开(公告)日：1982-03-04
申请号：DE2961891
申请日：1979-09-24
Applicant: IBM
Inventor： MITCHELL GLEN ROBERT , KEMPKE WILLIAM GEORGE , JONES EUGENE REESE , HOUDEK MERLE EDWARD , RANWEILER JAMES GREGORY
Abstract: Tagged pointer handling apparatus is provided for implementation in a computer system wherein a tag bit is provided for each word in main storage. This invention provides for the mixing of data and pointers within the same storage space, and provides a capability for checking and verifying the validity of the pointers without affecting the performance or operation of other instructions. Only the tag instructions can set the tag bits ON in main storage; all other instructions store data and set the corresponding tag bits OFF. Thus, if a pointer was modified inadvertently by one of these data handling instructions, the fact that the pointer is untagged is detected and the values in the pointer are treated as invalid when the pointer is used by the Load and Verify Tags instruction. Instructions to load, store, set, move, extract and insert tags are implemented by the tagged pointer handling apparatus. A Load and Verify Tags instruction checks the validity of the pointer and if valid, loads the pointer into a specified general purpose register. A Store and Set Tags instruction stores the value in a specified general purpose register into main storage and sets the associated tag bits ON. A Move and Set Tags instruction moves a word from one location in main storage to another or the same location in main storage and sets the associated tag bits ON. A Move Characters and Tags instruction moves a word and the associated tag bits from one storage location to another storage location. An Extract Tags instruction fetches each word from an operand in main storage, extracts the tag bits, compresses the tag bits to one tag bit per quadword, and stores the tag bits in main storage as data. An Insert Tags instruction fetches the tag bits stored in main storage as data, expands the tag bits to one tag bit per word, and inserts them on each associated word of an operand in main storage.
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