公开(公告)号：ES2237667T3

公开(公告)日：2005-08-01

申请号：ES02712095

申请日：2002-02-20

Applicant: IBM

Inventor： CALVIGNAC JEAN LOUIS ,  HEDDES MARCO ,  LOGAN JOSEPH FRANKLIN ,  VERPLANKEN FABRICE JEAN

IPC: H04L12/861 ,  H04L29/06 ,  H04L12/56

Abstract: Un sistema que comprende: - un procesador (100) configurado para tratar cuadros de datos, cuyo procesador comprende: - una unidad (110) de flujo de datos configurada para recibir y transmitir dichos cuadros de datos, y en la que cada uno de dichos cuadros de datos tiene un bloque de control de cuadro asociado, y cada uno de dichos bloques de control de cuadro comprende unos bloques de control primero y segundo; - una primera memoria (210) acoplada a dicha unidad de flujo de datos, cuya primera memoria comprende una primera unidad de control de memoria intermedia de cuadro, y dicha primera unidad de control de memoria intermedia de cuadro almacena información de campo para dicho primer bloque de control de dicho bloque de control de cuadro; y - un planificador de ejecución (130) acoplado a dicha unidad de flujo de datos, cuyo planificador está configurado para planificar cuadros de datos recibidos por dicha unidad de flujo de datos, y en el que dicho planificador comprende una segunda memoria (224), la cual comprende una segunda unidad de control de memoria intermedia de cuadro, y dicha segunda unidad de control de memoria intermedia de cuadro almacena información de campo para dicho segundo bloque de control del citado bloque de control de cuadro.

公开(公告)号：AU2002251004A1

公开(公告)日：2002-09-19

申请号：AU2002251004

申请日：2002-01-31

Applicant: IBM

Inventor： HANDLOGTEN GLEN HOWARD ,  CALVIGNAC JEAN LOUIS ,  LOGAN JOSEPH FRANKLIN ,  VERPLANKEN FABRICE ,  GOETZINGER WILLIAM JOHN ,  MIKOS JAMES FRANCIS ,  NORGAARD DAVID ALAN ,  HEDDES MARCO C

IPC: H04L12/56 ,  H04L12/44 ,  H04Q11/04

Abstract: A Network Processor (NP) is formed from a plurality of operatively coupled chips. The NP includes a Network Processor Complex (NPC) Chip coupled to a Data Flow Chip and Data Store Memory coupled to the Data Flow Chip. An optional Scheduler Chip is coupled to the Data Flow Chip. The named components are replicated to create a symmetric ingress and egress structure.

公开(公告)号：PL323387A1

公开(公告)日：1998-03-30

申请号：PL32338796

申请日：1996-05-03

Applicant: IBM

Inventor： COHEN ARIEL ,  HOLLAND WILLIAM GAVIN ,  LOGAN JOSEPH FRANKLIN ,  PARASH AVI

IPC: G06F13/36 ,  G06F12/06 ,  G06F13/14 ,  G06F15/16

Abstract: An adapter or add-in card for use in a peripheral component interconnect (PCI) computer includes a universal module which couples the card to the PCI bus. The module includes a set of selectively programmable configuration registers which are loaded by a microprocessor on the adapter. A circuit arrangement on the module issues a command which inhibits the PCI processor from accessing the configuration registers until fully loaded. Another circuit arrangement presents the Expansion ROM base address register as a 'read/write' register or a read only register with all bits set to logical "0 " to the PCI computer. If the Expansion ROM base address register is presented as a read only register with all bits set to "0 ", the PCI computer concludes that no Expansion ROM exists on the add-in card, and its contents are not shadowed into the memory of the PCI computer. This disabling of the Expansion ROM causes memory space to be conserved in the computer. If the Expansion ROM is presented as a read/write register with non-zero values, the PCI computer concludes that an Expansion ROM exists and "shadows" its contents into the memory of the PCI computer.

公开(公告)号：PL363474A1

公开(公告)日：2004-11-15

申请号：PL36347402

申请日：2002-02-20

Applicant: IBM

Inventor： CALVIGNAC JEAN LOUIS ,  HEDDES MARCO ,  LOGAN JOSEPH FRANKLIN ,  VERPLANKEN FABRICE JEAN

IPC: H04L12/861 ,  H04L12/00

Abstract: A method and system for reducing the number of accesses to memory to obtain the desired field information in frame control blocks. In one embodiment of the present invention, a system comprises a processor configured to process frames of data. The processor may comprise a data flow unit configured to receive and transmit frames of data, where each frame of data may have an associated frame control block. Each frame control block comprises a first and a second control block. The processor may further comprise a first memory coupled to the data flow unit configured to store field information for the first control block. The processor may further comprise a scheduler coupled to the data flow unit where the scheduler is configured to schedule frames of data received by data flow unit. The scheduler may comprise a second memory configured to store field information for the second control block.

公开(公告)号：PL182982B1

公开(公告)日：2002-05-31

申请号：PL34762796

申请日：1996-05-03

Applicant: IBM

Inventor： COHEN ARIEL ,  HOLLAND WILLIAM GAVIN ,  LOGAN JOSEPH FRANKLIN ,  PARASH AVI

IPC: G06F13/36 ,  G06F13/14 ,  G06F15/177 ,  G06F15/16 ,  G06F13/00

Abstract: An adapter or add-in card for using in a peripheral component interconnect (PCI) computer includes a universal module which couples the card to the PCI bus. The module includes a set of selectively programmable configuration registers which are loaded by a microprocessor on the adapter. A circuit arrangement on the module issues a command which inhibits the PCI processor from accessing the configuration registers until fully loaded.

公开(公告)号：PL323386A1

公开(公告)日：1998-03-30

申请号：PL32338696

申请日：1996-05-03

Applicant: IBM

Inventor： COHEN ARIEL ,  HOLLAND WILLIAM GAVIN ,  LOGAN JOSEPH FRANKLIN ,  PARASH AVI

IPC: G06F13/36 ,  G06F13/14 ,  G06F15/177 ,  G06F15/16 ,  G06F12/06

Abstract: An adapter or add-in card for using in a peripheral component interconnect (PCI) computer includes a universal module which couples the card to the PCI bus. The module includes a set of selectively programmable configuration registers which are loaded by a microprocessor on the adapter. A circuit arrangement on the module issues a command which inhibits the PCI processor from accessing the configuration registers until fully loaded.