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    METHOD FOR FORMING AN INTEGRATED INJECTION LOGIC CIRCUIT
    11.
    发明专利
    METHOD FOR FORMING AN INTEGRATED INJECTION LOGIC CIRCUIT 未知

    公开(公告)号：DE3174802D1

    公开(公告)日：1986-07-17

    申请号：DE3174802

    申请日：1981-06-23

    Applicant: IBM

    Inventor： ABBAS SHAKIR AHMED ,  MAGDO INGRID EMESE

    IPC: H01L21/822 ,  H01L21/033 ,  H01L21/331 ,  H01L21/8226 ,  H01L27/02 ,  H01L27/04 ,  H01L27/082 ,  H01L29/73 ,  H03K19/09 ,  H01L21/82 ,  H01L21/60

    Abstract: The method supplies self-aligned metal to silicon contacts and sub-micron contact-to-contact and metal-to-metal spacing in the Integrated Injection Logic (I L) or Merged Transistor Logic (MTL) technology. The insulation between the contacts and the metal is a pattern of dielectric material (24, 26, 30) having a thickness dimension in the order of a micron or less. … The method involves providing a silicon body (10, 12) and then forming a first insulating layer (16) on the silicon body. This layer is removed in areas designated to contain integrated injection logic devices. A layer (20) of highly doped polycrystalline silicon is formed thereover. The conductivity of the polycrystalline silicon is opposite to that of the silicon body. Openings are made in the polycrystalline silicon layer (20) by reactive ion etching which results in the structure having substantially horizontal and vertical surfaces. The openings are formed in areas designated to be the base of the lateral injector transistor of the integrated circuit. A second insulating layer (24, 26, 30) is then formed on both the substantially horizontal surfaces and substantially vertical surfaces. Reactive ion etching of this second insulating layer (24, 26, 30) substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions on the silicon body. The base of the lateral injector transistor is formed through the openings of the polycrystalline silicon layer (20). The structure is annealed to fully form the base of the transistor and to drive into the silicon body the opposite type impurities from the polycrystalline silicon layer (20) to thereby form the base regions for the vertical transistors of the integrated injection logic circuit. Additional openings and narrow dimensioned dielectric patterns are made in the polycrystalline silicon layer where the collector of the vertical transistor is to be formed. Finally the structure is contacted and planarized.

    14.
    发明专利
    未知

    公开(公告)号：DE2510757A1

    公开(公告)日：1975-10-23

    申请号：DE2510757

    申请日：1975-03-12

    Applicant: IBM

    Inventor： MAGDO INGRID EMESE ,  MAGDO STEVEN

    IPC: H05K3/46 ,  H01L21/48 ,  H01L21/768 ,  H01L23/14 ,  H01L23/498 ,  H01L23/522 ,  H01L23/538 ,  H01L21/96 ,  H01L21/92 ,  H01B5/14

    Abstract: An integrated circuit chip carrier with multi-level metallurgy, in which the effects of the metallurgy in causing elevation irregularitiies at the various levels of the structure are minimized, is produced by a method wherein a first plurality of levels of metallization patterns respectively separated by layers of dielectric material are first formed on a planar primary layer supported on a temporary substrate having a chemical etchability different from that of the layer. The primary layer is electrically insulative with respect to said metallization patterns. Then, a supporting layer is formed on the uppermost covering layer, after which the substrate is removed with a chemical etchant which preferentially etches the substrate away from the insulative layer. Next, an opposite plurality of levels of metallization patterns are formed on the side of the insulative layer opposite to the first formed metallization patterns. These opposite metallization patterns are also respectively separated by covering layers of dielectric material.

    METHOD FOR FORMING FIELD EFFECT TRANSISTOR INTEGRATED CIRCUITS HAVING A PATTERN OF NARROW DIMENSIONED DIELECTRIC REGIONS AND RESULTING STRUCTURES
    18.
    发明专利
    METHOD FOR FORMING FIELD EFFECT TRANSISTOR INTEGRATED CIRCUITS HAVING A PATTERN OF NARROW DIMENSIONED DIELECTRIC REGIONS AND RESULTING STRUCTURES 未知

    公开(公告)号：DE3175618D1

    公开(公告)日：1987-01-02

    申请号：DE3175618

    申请日：1981-06-23

    Applicant: IBM

    Inventor： ABBAS SHAKIR AHMED ,  MAGDO INGRID EMESE

    IPC: H01L29/78 ,  H01L21/033 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/321 ,  H01L21/336 ,  H01L21/768 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/10 ,  H01L27/108 ,  H01L29/41 ,  H01L21/31 ,  H01L21/00

    Abstract: A method for forming field effect transistor integrated circuits having a pattern of narrow dimensioned dielectric regions and more particularly a self-aligned metal process is described which achieves self-aligned metal to silicon contacts and submicron contact-to-contact and metal-to-metal spacing for field effect transistor integrated circuits. The insulation between the contacts and the metal is a pattern of dielectric material having a thickness dimension in the order of a micron or less. The metal and dielectric structure is substantially planar. The method for forming integrated circuits with this structure involves providing a silicon body (10) and then forming a first insulating layer (14) on a major surface of the silicon body. A layer of polycrystalline silicon (16) is formed thereover. Openings are made in the polycrystalline silicon layer by reactive ion etching which results in the structure having substantially horizontal surfaces (20) and substantially vertical surfaces (21). The openings can be in either the areas designated to be the gate regions or a PN junction region of the field effect transistors in the integrated circuit. A second insulating layer (22) is then formed on both the substantially horizontal surfaces (20) and substantially vertical surfaces (21). Reactive ion etching of this second insulating layer substantially removes the horizontal layers and provides a narrow dimensioned dielectric pattern of regions (22) on the major surface of the silicon body (10). The gate dielectric is either formed hereat or PN junctions are fabricated by diffusion or ion implantation techniques. The remaining polycrystalline silicon layer (16) is then removed by etching to leave the narrow dimensioned regions (22) on the major surface of the silicon body (10). A conductive layer is blanket deposited over the narrow dimensioned regions and areas in between to make contact to source drain PN regions and form the gate electrodes. A blanker layer of a plastic material over the conductive layer is used to planarize the surface. Reactive ion etching the plastic material and the conductive layer is continued until the tops of the narrow dimensioned regions are reached leaving the structure of patterns of metal or polycrystalline silicon filling the regions between the pattern of dielectric material having having a thickness dimension in the order of a micron or less. The gate, source and drain electrodes are thusly formed.

    METHOD FOR PRODUCING A VERTICAL BIPOLAR PNP TRANSISTOR STRUCTURE
    20.
    发明专利
    METHOD FOR PRODUCING A VERTICAL BIPOLAR PNP TRANSISTOR STRUCTURE 未知

    公开(公告)号：DE3070293D1

    公开(公告)日：1985-04-18

    申请号：DE3070293

    申请日：1980-12-04

    Applicant: IBM

    Inventor： MAGDO INGRID EMESE ,  RUPPRECHT HANS STEPHEN

    IPC: H01L21/225 ,  H01L21/331 ,  H01L21/74 ,  H01L21/8222 ,  H01L21/8228 ,  H01L27/06 ,  H01L27/082 ,  H01L29/08 ,  H01L29/73 ,  H01L29/36 ,  H01L21/265 ,  H01L27/08

    Abstract: Complementary, vertical bipolar NPN and PNP transistors are fabricated on the same monolithic semiconductor substrate which have matched high performance characteristics. A method for fabricating such complementary devices is also provided. In the method, a barrier region of a first conductivity type is formed on the surface of the monocrystalline semiconductor substrate doped with a second conductivity type. After an annealing heat treatment to drive in the doping ions of the barrier region, a collector region for one of the complementary transistors of a second conductivity type is formed within the barrier region. It is convenient to simultaneously form isolation regions of a second conductivity type in the substrate while forming the collector region. A collector region of a first conductivity type is then formed in the substrate for the other of the complementary transistors. The collector region for the other complementary transistor is formed within at least one other isolation region. An epitaxial layer of semiconductor material doped with ions of the first conductivity type is then formed on the surface of the substrate. To provide improved PNP transistor performance, the P-type emitter for the PNP transistor is formed prior to a last drive-in treatment by forming a polycrystalline silicon layer on the exposed surface of the base. The polycrystalline silicon is doped with a P-type dopant. Thereafter the transistor structure is subjected to conditions whereby the doping ions contained in the polycrystalline silicon layer are driven into the epitaxial layer to provide a shallow emitter region without effecting dislocations in the silicon lattice of the epitaxial layer.

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