公开(公告)号：DE3369427D1

公开(公告)日：1987-02-26

申请号：DE3369427

申请日：1983-10-05

Applicant: IBM

Inventor： HODGSON RODNEY TREVOR ,  JACKSON THOMAS NELSON ,  RUPPRECHT HANS STEPHAN ,  WOODALL JERRY MACPHERSON

IPC: C30B29/40 ,  C30B31/22 ,  H01L21/265 ,  H01L21/314 ,  H01L21/324

Abstract: Implanted impurity ions are activated in a compound semiconductor crystal wafer (1, 3), such as GaAs over a broad integrated circuit device area (4) by providing a uniform solid layer (5) (eg 10 ANGSTROM to 500 ANGSTROM thick) of the most volatile element of the compound over the surface (2) of the device area (4) and annealing the crystal wafer at a temperature of 800 DEG C to 900 DEG C for a period of 1 to 20 seconds. … The layer (5) of the most volatile element may either be formed on a backing substrate (6) or formed as a coating on the surface (2) of the crystal wafer (1, 3).

公开(公告)号：DE3474610D1

公开(公告)日：1988-11-17

申请号：DE3474610

申请日：1984-06-08

Applicant: IBM

Inventor： RUPPRECHT HANS STEPHAN ,  TIWARI SANDIP

IPC: H01L29/43 ,  H01L21/28 ,  H01L21/285 ,  H01L29/45 ,  H01L21/40

公开(公告)号：DE3172466D1

公开(公告)日：1985-11-07

申请号：DE3172466

申请日：1981-01-23

Applicant: IBM

Inventor： CAVALIERE JOSEPH RICHARD ,  HORNG CHENG TZONG ,  KONIAN RICHARD ROBERT ,  RUPPRECHT HANS STEPHAN ,  SCHWENKER ROBERT OTTO

IPC: H01L21/8222 ,  H01L21/033 ,  H01L21/285 ,  H01L21/331 ,  H01L21/762 ,  H01L27/06 ,  H01L29/73 ,  H01L29/732 ,  H01L29/72 ,  H01L21/76

公开(公告)号：DE3070813D1

公开(公告)日：1985-08-01

申请号：DE3070813

申请日：1980-10-15

Applicant: IBM

Inventor： HORNG CHENG TZONG ,  POPONIAK MICHAEL ROBERT ,  RUPPRECHT HANS STEPHAN ,  SCHWENKER ROBERT OTTO

IPC: H01L21/76 ,  H01L21/331 ,  H01L21/74 ,  H01L21/762 ,  H01L29/08 ,  H01L29/10 ,  H01L29/73 ,  H01L29/732 ,  H01L29/72 ,  H01L29/62 ,  H01L21/82

Abstract: A method for device fabrication disclosed is a self-aligned process. The device formed has small vertical as well as horizontal dimensions. The device region is surrounded by a deep oxide trench which has nearly vertical sidewalls. The deep trench extends from the epitaxial silicon surface through N+ subcollector region into the P substrate. The width of the deep trench is about 2 mu m to 3.0 mu m. A shallow oxide trench extending from the epitaxial silicon surface to the upper portion of the N+ subcollector separates the base and collector contact. The surface of the isolation regions and the silicon where the transistor is formed is coplanar. As shown in FIG. 1, the fabricated bipolar transistor has a mesa-type structure. The transistor base dimension is only slightly larger than the emitter. This small base area results in low collector-base capacitance which is a very important parameter in ultra-high performance integrated circuit devices. Contact to the transistor base in the disclosed structure is achieved by a thick heavily boron doped polysilicon layer which surrounds the emitter and makes lateral contact to the active base.

公开(公告)号：DE3163454D1

公开(公告)日：1984-06-14

申请号：DE3163454

申请日：1981-02-25

Applicant: IBM

Inventor： RUPPRECHT HANS STEPHAN ,  WOODALL JERRY MCPHERSON

IPC: H01L21/265 ,  H01L21/324

Abstract: Thermal decomposition is reduced and stoichiometry retained during annealing of a multiple element intermetallic semiconductor material by heating it in an environment with an excess of the most volatile constituent, in particular, when annealing a Si implanted GaAs wafer (58) while in proximity to InAs (50).

公开(公告)号：DE3070390D1

公开(公告)日：1985-05-02

申请号：DE3070390

申请日：1980-10-23

Applicant: IBM

Inventor： CHU WEI-KAN ,  MAGDO INGRID EMESE ,  RUPPRECHT HANS STEPHAN

IPC: H01L21/265 ,  H01L21/324 ,  H01L29/08 ,  H01L21/20

公开(公告)号：DE3166687D1

公开(公告)日：1984-11-22

申请号：DE3166687

申请日：1981-05-15

Applicant: IBM

Inventor： BRASLAU NORMAN ,  FREEHOUF JOHN LAWRENCE ,  PETTIT GEORGE DAVID ,  RUPPRECHT HANS STEPHAN ,  WOODALL JERRY MCPHERSON

IPC: H01L29/80 ,  H01L21/28 ,  H01L21/331 ,  H01L29/06 ,  H01L29/201 ,  H01L29/43 ,  H01L29/45 ,  H01L29/73 ,  H01L29/772 ,  H01L29/86 ,  H01L29/36 ,  H01L29/40