公开(公告)号：GB2552567A

公开(公告)日：2018-01-31

申请号：GB201705884

申请日：2015-09-15

Applicant: IBM

Inventor： JONATHAN DAVID BRADBURY ,  STEVEN CARLOUGH ,  REID COPELAND ,  MARCEL MITRAN

IPC: G06F9/30 ,  G06F5/00 ,  H03M7/24

Abstract: A method is provided for executing a machine instruction to convert data from a packed decimal format to a decimal floating point format. The method reads data in a packed decimal format from a memory that is communicatively coupled to a processor. The method converts the data in the packed decimal format into a decimal floating point format. The method writes the data converted into the decimal floating point format to one or more target registers of the processor

公开(公告)号：BR112014016333A8

公开(公告)日：2017-07-04

申请号：BR112014016333

申请日：2012-11-13

Applicant: IBM

Inventor： CHARLES GAINEY JR ,  ERIC MARK SCHWARZ ,  MARCEL MITRAN ,  REID COPELAND ,  STEVEN CARLOUGH ,  TIMOTHY SLEGEL

IPC: G06F9/30

公开(公告)号：BR112014031350A2

公开(公告)日：2017-06-27

申请号：BR112014031350

申请日：2012-11-26

Applicant: IBM

Inventor： CHRISTIAN JACOBI ,  DAN GREINER ,  MARCEL MITRAN ,  TIMOTHY SLEGEL

IPC: G06F9/06 ,  G06F9/44 ,  G06F9/54

公开(公告)号：BR112014016334A2

公开(公告)日：2017-06-13

申请号：BR112014016334

申请日：2012-11-13

Applicant: IBM

Inventor： CHARLES GAINEY JR ,  ERIC MARK SCHWARZ ,  MARCEL MITRAN ,  REID COPELAND ,  STEVEN CARLOUGH ,  TIMOTHY SLEGEL

IPC: G06F9/30

公开(公告)号：BR112014031335A2

公开(公告)日：2017-06-27

申请号：BR112014031335

申请日：2012-11-22

Applicant: IBM

Inventor： CHRISTIAN JACOBI ,  DAN GREINER ,  MARCEL MITRAN ,  TIMOTHY SLEGEL

IPC: G06F11/07

公开(公告)号：GB2517876B

公开(公告)日：2017-03-22

申请号：GB201500043

申请日：2013-05-20

Applicant: IBM

Inventor： BRIAN ROBERT PRASKY ,  ALEXANDER VASILEVSKIY ,  JAMES JOSEPH BONANNO ,  JORAN SIU ,  MARCEL MITRAN ,  TIMOTHY SLEGEL

IPC: G06F9/38 ,  G06F9/30

公开(公告)号：GB2539601A

公开(公告)日：2016-12-21

申请号：GB201617085

申请日：2015-02-23

Applicant: IBM

Inventor： DAN GREINER ,  TIMOTHY SLEGEL ,  CHRISTIAN JACOBI ,  DONALD WILLIAM SCHMIDT ,  MARCEL MITRAN ,  CHARLES GAINEY JR

IPC: G06F9/30 ,  G06F9/38

Abstract: A delay facility is provided in which program execution may be delayed until a predefined event occurs, such as a comparison of memory locations results in a true condition, a timeout is reached, an interruption is made pending or another condition exists. The delay facility includes one or more compare and delay machine instructions used to delay execution. The one or more compare and delay instructions may include a 32-bit compare and delay (CAD) instruction and a 64-bit compare and delay (CADG) instruction.