公开(公告)号：CA2337784A1

公开(公告)日：2001-08-29

申请号：CA2337784

申请日：2001-02-15

Applicant: IBM

Inventor： GLOSSNER CLAIR JOHN III ,  HOKENEK ERDEM ,  MELTZER DAVID ,  MOUDGILL MAVAN

IPC: G06F17/16 ,  G06F9/345 ,  G06F12/00 ,  G06F15/78 ,  G06F15/80

Abstract: A system and method for processing operations that use data vectors each comprising a plurality of data elements, in accordance with the present invention, includ es a vector data file comprising a plurality of storage elements for storing data elements of the data vectors. A pointer array is coupled by a bus to the vector data file. The pointer array includes a plurality of entries wherein each entry identifies at least one storage element in the vector data file. The at least one storage element stores at least one data element of the data vectors, wherein for at least one particular entry in the pointer array, the at least one storage element identified by the particular entry has an arbitrary starting address in the vector data file.

公开(公告)号：AU2003249378A1

公开(公告)日：2004-01-19

申请号：AU2003249378

申请日：2003-06-24

Applicant: IBM

Inventor： MELTZER DAVID ,  MOUDGILL MAYAN ,  GLOSSNER CLAIR JOHN III ,  HOKENEK ERDEM

IPC: G06F9/345 ,  G06F15/78 ,  G06F15/80

Abstract: A digital signal processor (DSP) includes dual SIMD units that are connected in cascade, and wherein results of a first SIMD stage of the cascade may be stored in a register file of a second SIMD stage in the cascade. Each SIMD stage contains its own resources for storing operands and intermediate results (e.g., its own register file), as well as for decoding the operations that may be executed in that stage. Within each stage, hardware resources are organized to operate in SIMD manner, so that independent SIMD operations can be executed simultaneously, one in each stage of the cascade. Intermediate operands and results flowing through the cascade are stored at the register files of the stages, and may be accessed from those register files. Data may also be brought from memory directly into the register files of the stages in the cascade.

公开(公告)号：AU2002257172A1

公开(公告)日：2003-11-03

申请号：AU2002257172

申请日：2002-04-19

Applicant: IBM

Inventor： GLOSSNER CLAIR JOHN III ,  HOKENEK ERDEM ,  MELTZER DAVID ,  MOUDGILL MAYAN ,  ALTMAN ERIK R

IPC: G06F1/32 ,  G06F9/45 ,  G06F15/78

Abstract: A microprocessor includes a logic circuit. A selection device is coupled to the logic circuit, and the selection device procides switching of on/off states of the logic circuit based on a stored logical value. A program instruction is included which sets the stored logical value control the on/off states of the logic circuit based on anticipated usage of the logical circuit in accordance with an instruction sequence of the microprocessor.

公开(公告)号：DE3584318D1

公开(公告)日：1991-11-14

申请号：DE3584318

申请日：1985-05-21

Applicant: IBM

Inventor： AICHELMANN JR ,  BLUMBERG REX HAROLD ,  MELTZER DAVID ,  POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  SPARACIO FRANK JOHN

IPC: G06F12/08 ,  G06F12/0897

公开(公告)号：DE3176988D1

公开(公告)日：1989-03-16

申请号：DE3176988

申请日：1981-12-30

Applicant: IBM

Inventor： MELTZER DAVID

IPC: G06F11/10 ,  H03M13/13

公开(公告)号：DE3174603D1

公开(公告)日：1986-06-19

申请号：DE3174603

申请日：1981-02-25

Applicant: IBM

Inventor： MELTZER DAVID

IPC: G06F3/06 ,  G06F12/08 ,  G06F12/10 ,  G06F13/10 ,  G06F13/12 ,  G06F13/00

Abstract: A data processing system and a method of operating the system to transfer data between the main store and a secondary paging store are described. The operations to prepare the secondary paging store for the data transfer relative to the main store are overlapped in time with chaining operations of an input-output channel inter-connecting the stores for preparing a command defining the transfer operation. The paging store is organized for sequential access to page records and the operations to prepare the paging store include a calculation of a "roll mode" displacement factor which defines a randomly chosen displacement position in a designated page area for beginning the transfer with minimized latency. This displacement factor is calculated as a function of channel operational characteristics as well as the bit timing rate of the paging store. The displacement calculation is also adapted for a paging store having different timing rates for transferring data and regenerating stored data. The displacement factor is stored in a buffer register and conditionally transferred to the channel when the channel next selects the paging store in association with the chained command. The transfer of the displacement factor is conditioned on the timing of the channel selection relative to the accessibility timing of the displacement position. If the selection is late the response to the selection is delayed until a new factor is calculated. Such re-calculations will be relatively infrequent in a system which is not overloaded with channel contention activity.