公开(公告)号：AU534448B2

公开(公告)日：1984-02-02

申请号：AU5374779

申请日：1979-12-12

Applicant: IBM

Inventor： BOURKE DONALL GARRAID ,  MENDELSON RICHARD NEIL ,  MADRUGA LUIS

IPC: G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F9/18

公开(公告)号：AU5374779A

公开(公告)日：1980-06-26

申请号：AU5374779

申请日：1979-12-12

Applicant: IBM

Inventor： BOURKE DONALL GARRAID ,  MENDELSON RICHARD NEIL ,  MADRUGA LUIS

IPC: G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F9/18

公开(公告)号：IN179963B

公开(公告)日：1998-01-03

申请号：IN645DE1990

申请日：1990-06-26

Applicant: IBM

Inventor： BONEVENTO FANCIS MICHACE ,  CHISHOIM DOUGLAS RODERICM ,  DODDS SAMMY DAVES ,  DESAI DHARUVKUMAR MANAROHARDAS ,  MANDESE ERNEST NEISH ,  MCNEIL ANDREW BOYCL ,  MENDELSON RICHARD NEIL

IPC: G06C21/00

公开(公告)号：PE3691A1

公开(公告)日：1991-02-15

申请号：PE17079390

申请日：1990-06-14

Applicant: IBM

Inventor： HEATH CHESTER ASBURY ,  MENDELSON RICHARD NEIL ,  BONEVENTO FRANCIS MICHAEL ,  MANDESE ERNEST NELSON

IPC: G06F9/46 ,  G06F9/48 ,  G06F13/24

Abstract: CARACTERIZADA POR ESTAR REFERIDA A LA GESTION DE MULTIPLES INTERRUPCIONES LOGICAS DE COMANDOS INDIRECTOS EN UNA INTERRUPCION FISICA DESDE UN SUBSISTEMA A UN PROCESADOR CENTRAL. EL PROCESADOR CENTRAL PUEDE BORRAR MULTIPLES INTERRUPCIONES LOGICAS DESDE UN DISPOSITIVO LOGICO, DADO EN EL SUBSISTEMA CON UN SOLO COMANDO DE REINICIALIZACION DE INTERRUPCIONES

公开(公告)号：AU1027883A

公开(公告)日：1983-07-21

申请号：AU1027883

申请日：1983-01-11

Applicant: IBM

Inventor： MENDELSON RICHARD NEIL ,  NEAL DOUGLAS MARCUS O ,  SHARP LEO ALVIN

IPC: G06F13/38 ,  G06F13/12 ,  G06F13/28 ,  G06F3/00

Abstract: There is disclosed apparatus and a method for extending a parallel channel of the host processor over a serial link to a remote peripheral device. The apparatus includes a microprocessor within I/O channel extension logic which responds to either instructions or data from a host processor. The instructions are of the type commanding the I/O device to perform a specific operation and the data is provided in response to requests for data from the I/O device. The channel extension logic is coupled to the host processor's channel and thus is able to obtain data from the host storage by cycle steal techniques. Within the channel extension logic are means to serialize the information and transmit it in a serial manner over the link. The microprocessor within the channel extension logic creates a frame, including a control byte, which identifies the type of information followed by the data, which frame is then communicated over the serial link to the I/O device. The I/O device also includes a microprocessor and associated logic which responds to the frames communicated by the channel extension logic and generates a frame consisting of a control byte identifying the information type and associated data which is then communicated back over the serial link to the channel extension logic to request action by the channel extension logic or indicate completion of the operation. The I/O device may, for instance, request data be obtained from or stored in the host memory by cycle steal techniques and thereby utilize the features of the host and host channel despite only being coupled thereto by a serial link.