公开(公告)号：ZA201604938B

公开(公告)日：2019-02-27

申请号：ZA201604938

申请日：2016-07-15

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY JR CHARLES (DECEASED) ,  JACOBI CHRISTIAN

Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer-implemented method for dynamic enablement of multithreading in a configuration is provided. The configuration includes a core configurable between a single thread (ST) mode and a multithreading (MT) mode, where the ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.

公开(公告)号：HUE037896T2

公开(公告)日：2018-09-28

申请号：HUE15711701

申请日：2015-03-16

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY

IPC: G06F9/50 ,  G06F9/38

公开(公告)号：ES2673903T3

公开(公告)日：2018-06-26

申请号：ES15711701

申请日：2015-03-16

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY

IPC: G06F9/50 ,  G06F9/38

Abstract: Un sistema informático, que comprende: una configuración (102) que comprende un núcleo configurable entre un modo de subproceso único (ST) y un modo de subprocesamiento múltiple (MT), el modo ST que se dirige a un subproceso primario y el modo MT que se dirige al subproceso primario y a uno o más subprocesos secundarios sobre recursos compartidos del núcleo; y una facilidad de subprocesamiento múltiple (103) configurada para controlar la utilización de la configuración, en donde la facilidad de subprocesamiento múltiple está adaptada para: acceder al subproceso primario en el modo ST usando un valor de dirección de núcleo; conmutar del modo ST al modo MT; y acceder al subproceso primario o a uno del uno o más subprocesos secundarios en el modo MT, y caracterizado por que la facilidad de subprocesamiento múltiple está adaptada para acceder al subproceso primario o a uno del uno o más subprocesos secundarios en el modo MT usando un valor de dirección expandido, comprendiendo el valor de dirección expandido el valor de dirección de núcleo concatenado con un valor de dirección de subproceso.

公开(公告)号：DK3123326T3

公开(公告)日：2018-06-25

申请号：DK15711701

申请日：2015-03-16

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SLEGEL TIMOTHY ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON

IPC: G06F9/50

公开(公告)号：CA2800640C

公开(公告)日：2017-12-12

申请号：CA2800640

申请日：2010-11-08

Applicant: IBM

Inventor： GREINER DAN ,  OSISEK DAMIAN LEO ,  SLEGEL TIMOTHY ,  HELLER LISA

IPC: G06F9/455 ,  G06F9/30

Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.

公开(公告)号：AU2015238663B2

公开(公告)日：2017-05-25

申请号：AU2015238663

申请日：2015-03-16

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY JR CHARLES

IPC: G06F9/46

Abstract: THREAD CONTEXT RESTORATION IN A MULTITHREADING COMPUTER SYSTEM Amultithreading computer system includesa configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method including disabling one or more secondary threads based on switching from MT mode to ST mode. A thread context of secondary threads is made unavailable to programs. Based on a last-set program-specified maximum thread-id indicating MT, the thread context is obtained by a) executing a set MT instruction to resume the MT mode, and b) based on being in the resumed MT mode, accessing the thread context.

公开(公告)号：AU2015238632A1

公开(公告)日：2016-08-04

申请号：AU2015238632

申请日：2015-03-19

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY JR CHARLES ,  JACOBI CHRISTIAN

IPC: G06F9/50 ,  G06F9/38

Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.

公开(公告)号：CA2940990A1

公开(公告)日：2015-10-01

申请号：CA2940990

申请日：2015-03-16

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY CHARLES JR

IPC: G06F9/46

Abstract: A computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method that includes accessing the primary thread in the ST mode using a core address value and switching from the ST mode to the MT mode. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value, where the expanded address value includes the core address value concatenated with a thread address value.

公开(公告)号：AU2010355865B2

公开(公告)日：2014-04-03

申请号：AU2010355865

申请日：2010-11-08

Applicant: IBM

Inventor： SITTMANN III GUSTAV ,  CRADDOCK DAVID ,  GREGG THOMAS ,  SCHMIDT DONALD WILLIAM ,  BELMAR BRENTON FRANCOIS ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  TARCZA RICHARD ,  EASTON JANET

IPC: G06F9/48

Abstract: The conditions under which adapter interruptions are made pending are controlled. Responsive to an interruption being presented to an operating system, subsequent interruptions are suppressed on all central processing units in the configuration. The operating system processes the interruption, including examining and processing indicators of reported events until the operating system discontinues the suppression. This enables the operating system to control the number of pending interruptions and the number of processors processing those interruptions.

公开(公告)号：ZA201209646B

公开(公告)日：2013-08-28

申请号：ZA201209646

申请日：2012-12-19

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  OSISEK DAMIAN LEO ,  HELLER LISA

IPC: G06F20060101

Abstract: In a processor supporting execution of a plurality of functions of an instruction, an instruction blocking value is set for blocking one or more of the plurality of functions, such that an attempt to execute one of the blocked functions, will result in a program exception and the instruction will not execute, however the same instruction will be able to execute any of the functions that are not blocked functions.