公开(公告)号：CA909862A

公开(公告)日：1972-09-12

申请号：CA909862D

Applicant: IBM

Inventor： OTTAWAY GERALD H ,  DICKERSON JACK A

IPC: H02M3/07 ,  H02M7/12

公开(公告)号：CA735093A

公开(公告)日：1966-05-24

申请号：CA735093D

Applicant: IBM

Inventor： OTTAWAY GERALD H

公开(公告)号：CA2036266C

公开(公告)日：1995-09-26

申请号：CA2036266

申请日：1991-02-13

Applicant: IBM

Inventor： KERKER ROBERT P JR ,  OTTAWAY GERALD H ,  PEETS MICHAEL T

IPC: G06F17/50 ,  G06T15/00 ,  G06T17/10 ,  G09G5/00

Abstract: A hierarchical data storage schema is provided which associatively links a master solid object model in a graphics data processing system to a solid model of a sectioning object. The associative linking provides the capability of automatically generating sectioned views when the master object is modified. These views are generated at the operator's request without the necessity of having to apply sectioning objects to each one of the subsequent views. An interactive facility is provided for creating such structures.

公开(公告)号：CA2036266A1

公开(公告)日：1991-09-20

申请号：CA2036266

申请日：1991-02-13

Applicant: IBM

Inventor： KERKER ROBERT P JR ,  OTTAWAY GERALD H ,  PEETS MICHAEL T

IPC: G06F17/50 ,  G06T15/00 ,  G06T17/10 ,  G09G5/00

公开(公告)号：FR2276738A1

公开(公告)日：1976-01-23

申请号：FR7515093

申请日：1975-05-06

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  HILLER RICHARD ,  OTTAWAY GERALD H ,  WINKLER VAUGHN D

IPC: G06F7/48 ,  G06K9/46 ,  H03K19/173 ,  H03K19/177 ,  H03K19/20 ,  G06K9/00 ,  G11C19/14

Abstract: 1476880 Character recognition programmable logic circuit INTERNATIONAL BUSINESS MACHINES CORP 17 April 1975 [24 June 1974 (2)] 15770/75 Heading G4R A logic circuit arrangement for use in a character recognition device has a shift register SR1- 48 feeding a plurality of programmable logic circuits P AND 1-48. Data representing for instance a scanning matric 40 Î 24 is fed serially to a 960 bit shift register formed of 48 20 bit sections. Each section feeds a plurality of programmable AND circuits 1-48 each of which produces a one bit output which is fed back to 64 feedback latches which also feed the P AND circuits. Selected P AND circuits 37-48 also feed output latches. The P AND circuits may be as shown in Fig. 8C for a three input gate in which latches 115, 116, 124, 125, 133, 134 are set to determine the logic operation. If both latches for an input are zero the inverters, e.g. 119, 120 for input A feed "1"s to AND gate 123. If only one is zero then either A or A is fed to gate 123. OR functions are produced using inverters and de Morgan's theorem A - B = A + B. The shift register may contain dummy registers which are not connected to the logic circuits to reduce the number of connections required while still storing the same number of bits. Thus portions of an area are processed alternately (Fig. 14, not shown).

公开(公告)号：CA763107A

公开(公告)日：1967-07-11

申请号：CA763107D

Applicant: IBM

Inventor： TERTEL KLAUS ,  OTTAWAY GERALD H