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公开(公告)号：CA1030659A
公开(公告)日：1978-05-02
申请号：CA229600
申请日：1975-06-18
Applicant: IBM
Inventor： BOSSEN DOUGLAS C , HSIAO MU-YUE , PATEL ARVIND M
Abstract: This specification describes an error correction system for a high density memory made up of a number of monolithic wafers each containing a plurality of arrays that are addressed thru circuitry and wiring contained on that wafer. The storage bits on the wafers are functionally divided into a number of blocks each containing a plurality of words. The words of each block are on several wafers with each word made up of a plurality of arrays on a single array wafer. Each word in a block is protected by a similar error correction double multiple error detection code. The block is further protected by two additional check words made up using a b-adjacent code. Each byte in the check words protects one byte position of the words of the block. When a single error is detected in any word by the SEC-MED code the code corrects the error. If a multiple error is detected, the multiple error signal points to the word in error to be corrected by the b-adjacent code check words.
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公开(公告)号：FR2280949A1
公开(公告)日：1976-02-27
申请号：FR7518982
申请日：1975-06-09
Applicant: IBM
Inventor： PATEL ARVIND M
Abstract: 1472669 Error correction system INTERNATIONAL BUSINESS MACHINES CORP 15 May 1975 [30 July 1974] 20476/75 Heading G4C A sequence of n x k (16 x 13) data bytes D has n pairs of check bytes appended thereto, each check byte pair being generated from a different k data bytes spaced n bytes apart in the sequence according to the equations and as disclosed in Specification 1,369,725, and a periodic synchronization burst (SN-1B)- (SN-15B) of non-data pulses is added after every n data bytes. The individual digits of each byte may be recorded as bit pairs as disclosed in Specification 1,440,106 and each synchronization burst, whose purpose is to prevent an error causing loss of synchronization and consequential error over a longer span than the actual span of the error, may be formed by an invalid sequence of bit pairs which violates predetermined charge constraints imposed on the data fit sequences but does not violate minimum or maximum run length constraints. Recording or parallel longitudinal or diagonal tracks of magnetic tape is discussed.
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公开(公告)号：CA1309495C
公开(公告)日：1992-10-27
申请号：CA603836
申请日：1989-06-23
Applicant: IBM
Inventor： EGGENBERGER JOHN S , HODGES PAUL , PATEL ARVIND M
Abstract: A method is disclosed for correcting multibyte errors in a magnetic medium on which data is recorded in variable length blocks that comprise subblocks of data bytes and corresponding check bytes and include error correction code (ECC) for which ECC syndromes are generated during reading. A sequence of N sequential parity check bytes is written at the end of each block. After ECC syndromes are generated during reading, parity syndromes are generated by comparing parity check bytes computed from data bytes and check bytes as read with the parity check bytes as written. When a long-burst error occurs, a pointer points to the first of the N consecutive bytes in a block that could have been influenced by the error burst. After correcting correctable errors in all subblocks not affected by the N bytes identified by the pointer, and adjusting the parity syndromes for errors thus corrected, the adjusted parity syndromes are used to correct the errors in the N bytes indicated by the pointer. Unused ECC syndromes are then adjusted for errors corrected by the adjusted parity syndromes and used to correct all correctable errors then remaining. SA9-88-041
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公开(公告)号：CA1308811C
公开(公告)日：1992-10-13
申请号：CA572185
申请日：1988-07-15
Applicant: IBM
Inventor： MARCUS BRIAN H , PATEL ARVIND M , SIEGEL PAUL H
IPC: H03M7/14 , H03M5/14 , H03M13/23 , H04L25/497
Abstract: SA986-013 METHOD AND APPARATUS FOR IMPLEMENTING A PRML CODE A rate 8/9, constrained partial response class IV code having run length limitation parameters (0,3/5) is provided for any partial response (PR) signaling system employing maximum likelihood (ML) detection.
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Patent Agency Ranking
公开(公告)号：CA1262189A
公开(公告)日：1989-10-03
申请号：CA532490
申请日：1987-03-19
Applicant: IBM
Inventor： EGGENBERGER JOHN S , PATEL ARVIND M
Abstract: METHOD AND APPARATUS FOR IMPLEMENTING OPTIMUM PRML CODES Rate 8/9, constrained codes having run length limitation parameters (0, 4/4) and (0, 3/63 are provided for any partial response (PR) signaling system employing maximum likelihood (ML) detection.
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公开(公告)号：CA1097799A
公开(公告)日：1981-03-17
申请号：CA299885
申请日：1978-03-29
Applicant: IBM
Inventor： EIGE JOHN J , PATEL ARVIND M , ROBERTS SPENCER D , STEDMAN DAVID
Abstract: TAPE MOTION CONTROL FOR REEL-TO-REEL DRIVE High tape acceleration rates are achieved in an unbuffered capstanless tape drive system by a tape motion control apparatus employing separate drive motors for each reel of a reel-to-reel tape transport. Tape moves from one reel past a read/write head and a tape tension sensor to the other reel, there being no tachometer in the tape feed path. A tachometer on one reel shaft provides a large number of pulses per revolution which pulses are counted by a counter; and a tachometer on the other reel shaft provides only one pulse per revolution, which pulse gates out the count then accumulated in the counter for actuating means to provide motor acceleration currents of a magnitude corresponding to said accumulated count according to a predetermined servo algorithm for controlling rotation of both reels. A tape radius constant corresponding to the actual length and thickness of tape in the system is calculated during initial wrap of tape onto the takeup reel. Tension is tightly controlled by an analog tension sensor and servo system.
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公开(公告)号：FR2412913A1
公开(公告)日：1979-07-20
申请号：FR7833617
申请日：1978-11-21
Applicant: IBM
Inventor： PATEL ARVIND M
Abstract: Where data is recorded on logically independent sets of parallel channels or tracks, the correction of error of very long (infinite) length cannot be advantageously treated by conventional coding methods unlike finite length error such as single shot or burst noise. To ensure the correction of channels in error from data recovered from a multi-channel storage medium, a fixed number of channels per set are dedicated to error checking bits. In this invention, more than the usual number of channels in error in any one set are made correctable by adaptively reallocating the unused redundant channels in the other set. This is accomplished by encoding and recording in the first redundant channel in each set vertical parity checks limited to that set while encoding and recording in the second redundant channel of each set, the parity of data taken over both sets of channels in a predetermined positively or negatively sloped direction. With this type of parity information so recorded, then the data obtained from up to three known erroneous channels in any one set may be corrected, provided that two sets together aggregate not more than four channels in error. Advantageously, the vertical and cross-parity checking information can also be used to generate an internal channel-in-error pointer for the first erroneous track in each set. Additionally, this data can be made to yield a second internal channel-in-error pointer in at least one of the sets. Lastly, error patterns are identified upon decoding at the intersection of at least two error syndromes one of which is derived from cross-parity checking bits.
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公开(公告)号：FR2325105A1
公开(公告)日：1977-04-15
申请号：FR7413430
申请日：1974-04-10
Applicant: IBM
Inventor： BOSSEN DOUGLAS C , HONG SE JUNE , HSIAO MU-YUE , PATEL ARVIND M
Abstract: Errors in code words fetched from memory or utilized in some other device are detected by apparatus distributed throughout the memory and then corrected. Illustratively, a 72-bit parallel code word, comprising a 64-bit information portion and an 8-bit check portion is fetched from the memory. The check bit generator consists of 8 identical modular units which, in the case of use in a memory, can be located at different locations within the memory. The identical modular units are connected in accordance with connections determined by an H matrix. The H matrix is partitioned into eight equal sections associated with eight information bits forming a byte and a single check bit. The rows of each partition or section are cyclically permutated from section to section. For example, the first row of the first section becomes the second row of the second section, etc. Each partition of the H matrix contains the same number of 1's and each row within a partition is part of a different code group. Each of the identical modular arrangements contains a logic circuit grouping. The input information byte bits are connected to the circuits of the logic grouping so as to produce as circuit outputs the parities of the part of the code groups in the partition or section associated with the module. The identical modular units also contain circuitry to receive the partial code groups parities from the other modular units concerned with the same code group. These partial code group parities and the partial code group parity of the respective module are combined to provide the check bit for the particular module. The partial code group parity outputs from the module are transmitted to the successive other modules to form the partial code group parity inputs for the respective modules. After the information has been utilized such as writing in storage, the information bits and check bits are read into an error detector which compares the check bits generated from the received information bits with the received check bits. An error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The error detector can consist of the same identical modular units as the check bit generator.
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公开(公告)号：FR2282675A1
公开(公告)日：1976-03-19
申请号：FR7518985
申请日：1975-06-09
Applicant: IBM
Inventor： BOSSEN DOUGLAS C , HSIAO MU-YUE , PATEL ARVIND M
Abstract: This specification describes an error correction system for a high density memory made up of a number of monolithic wafers each containing a plurality of arrays that are addressed thru circuitry and wiring contained on that wafer. The storage bits on the wafers are functionally divided into a number of blocks each containing a plurality of words. The words of each block are on several wafers with each word made up of a plurality of arrays on a single array wafer. Each word in a block is protected by a similar error correction double multiple error detection code. The block is further protected by two additional check words made up using a b-adjacent code. Each byte in the check words protects one byte position of the words of the block. When a single error is detected in any word by the SEC-MED code the code corrects the error. If a multiple error is detected, the multiple error signal points to the word in error to be corrected by the b-adjacent code check words.
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