公开(公告)号：DE69030931D1

公开(公告)日：1997-07-24

申请号：DE69030931

申请日：1990-02-06

Applicant: IBM

Inventor： EMMA PHILIP GEORGE ,  KNIGHT JOSHUA WILSON ,  POMERENE JAMES HERBERT ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  SPARACIO FRANK JOHN

IPC: G06F9/38

公开(公告)号：DE69023568T2

公开(公告)日：1996-06-13

申请号：DE69023568

申请日：1990-05-09

Applicant: IBM

Inventor： EMMA PHILIP GEORGE ,  KNIGHT JOSHUA WILSON ,  POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN

IPC: G06F12/08

Abstract: A cache memory system develops an optimum sequence for transferring data values between a main memory (50) and a line buffer (30) internal to the cache (20). At the end of a line transfer, the data in the line buffer (30) is written into the cache memory (20) as a block. Following an initial cache miss, the cache memory system monitors the sequence of data requests received for data in the line that is being read in from main memory (50). If the sequence being used to read in the data causes the processor (10) to wait for a specific data value in the line, a new sequence is generated in which the specific data value is read at an earlier time in the transfer cycle. This sequence is associated with the instruction that caused the first miss and is used for subsequent misses caused by the instruction. If, in the process of handling a first miss related to a specific instruction, a second miss occurs which is caused by the same instruction but which is for data in a different line of memory, the sequence associated with the instruction is marked as an ephemeral miss. Data transferred to the line buffer (30) in response to an ephemeral miss is not stored in the cache memory (20) and limited to that portion of the line accessed within the line buffer (30).

公开(公告)号：DE3750306D1

公开(公告)日：1994-09-08

申请号：DE3750306

申请日：1987-04-24

Applicant: IBM

Inventor： POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  SPARACIO FRANK JOHN

IPC: G06F9/38

Abstract: A method and apparatus for controlling access to its general purpose registers (GPR) by a high end machine configuration including a plurality of execution units within a single central processing unit (CPU). The invention allows up to "N" execution units to be concurrently executing up to "N" instructions using the same general purpose register (GPR) sequentially or different general purpose registers (GPR) concurrently as either SINK or SOURCE while at the same time preserving the logical integrity of the data supplied to the execution units. The use of the invention allows a higher degree of parallelism in the execution of the instructions than would otherwise be possible if only sequential operations were performed. A series of special purpose tags are associated with each general purpose register (GPR) and execute unit. These tags are used together with control circuitry both within the general purpose registers (GPR), within the individual execute units and within the instruction decode unit, which permit the multiple use of the registers to be accomplished while maintaining the requisite logical integrity.

公开(公告)号：DE3884101D1

公开(公告)日：1993-10-21

申请号：DE3884101

申请日：1988-04-21

Applicant: IBM

Inventor： EMMA PHILIP GEORGE ,  KNIGHT III JOSHUA WILSON ,  POMERENE JAMES HERBERT ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  SPARACIO FRANK JOHN

IPC: G06F9/38 ,  G06F15/16 ,  G06F15/177

公开(公告)号：DE3071119D1

公开(公告)日：1985-10-31

申请号：DE3071119

申请日：1980-06-24

Applicant: IBM

Inventor： POMERENE JAMES HERBERT

IPC: G06F9/38

Abstract: A method and a computing machine for concurrently executing (A, B, C, D) instructions that have been compiled into a multi-instruction word (10) comprised of a group of n instructions (12, 14, 16, 18), where n is an integer. The group must not demand more than a predetermined number of data and instruction fetches (38, 40, 26), or more than one store operation (60). If a branch instruction occurs, it must always be at the end of the group. Each instruction utilizes a different set of data (6, 48, 56, 58) for purposes of instruction execution.

公开(公告)号：DE69023568D1

公开(公告)日：1995-12-21

申请号：DE69023568

申请日：1990-05-09

Applicant: IBM

Inventor： EMMA PHILIP GEORGE ,  KNIGHT JOSHUA WILSON ,  POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN

IPC: G06F12/08

Abstract: A cache memory system develops an optimum sequence for transferring data values between a main memory (50) and a line buffer (30) internal to the cache (20). At the end of a line transfer, the data in the line buffer (30) is written into the cache memory (20) as a block. Following an initial cache miss, the cache memory system monitors the sequence of data requests received for data in the line that is being read in from main memory (50). If the sequence being used to read in the data causes the processor (10) to wait for a specific data value in the line, a new sequence is generated in which the specific data value is read at an earlier time in the transfer cycle. This sequence is associated with the instruction that caused the first miss and is used for subsequent misses caused by the instruction. If, in the process of handling a first miss related to a specific instruction, a second miss occurs which is caused by the same instruction but which is for data in a different line of memory, the sequence associated with the instruction is marked as an ephemeral miss. Data transferred to the line buffer (30) in response to an ephemeral miss is not stored in the cache memory (20) and limited to that portion of the line accessed within the line buffer (30).

公开(公告)号：DE3751474D1

公开(公告)日：1995-09-28

申请号：DE3751474

申请日：1987-02-05

Applicant: IBM

Inventor： EMMA PHILIP GEORGE ,  POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  SPARACIO FRANK JOHN

IPC: G06F9/38

公开(公告)号：DE3586635D1

公开(公告)日：1992-10-22

申请号：DE3586635

申请日：1985-02-28

Applicant: IBM

Inventor： POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN ,  SPARACIO FRANK JOHN

IPC: G06F12/08

Abstract: An efficient prefetching mechanism is disclosed for a system comprising a cache. In addition to the normal cache directory (11), a two-level shadow directory (13, 15) is provided. When an information block is accessed, a parent identifer (P) derived from the block address is stored in the top level (13) of the shadow directory. The address of a subsequently accessed block (Q) is stored in the second level (15) of the shadow directory, in a position associated with the first-level position of the respective parent identifier. … With each access to an information block, a check is made whether the respective parent identifier (P) is already stored in the first level of the shadow directory. If it is found, then the descendant address (Q) from the associated second-level position is used to prefetch an information block to the cache if it is not already resident therein. This mechanism avoids with high probability the occurence of cache misses.

公开(公告)号：DE3172029D1

公开(公告)日：1985-10-03

申请号：DE3172029

申请日：1981-09-09

Applicant: IBM

Inventor： POMERENE JAMES HERBERT ,  RECHTSCHAFFEN RUDOLPH NATHAN

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/08

Abstract: An information processing unit and storage system comprising at least one low speed, high capacity main memory having relatively long access time and including a plurality of data pages stored therein and at least one high speed, low capacity Cache memory means having a relatively short access time and adapted to store a predetermined plurality of subsets of the information stored in said main memory data pages. Instruction decoding means are located in the communication channel between the main Memory and the Cashe which are operative to at least partially decode instructions being transferred from main Memory to Cache. The at least partial decoding comprising expanding the instruction format from that utilized in the main Memory storage to one more readily executable by the processor prior to storing said instructions in the Cache. Said decoding means includes a logic circuit means for determining whether a given instruction is susceptible of partial decoding and means for determining that a particular instruction has already been partially decoded (i.e., after a first accessing of said instruction by the processor from Cache). In the preferred embodiment the assumption is made that the system utilizes separate Cache storage means for data and instructions respectively whereby only instructions being transferred from main Memory to Cache will pass through said decoding means.