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    4.
    发明专利
    未知

    公开(公告)号：DE69023568D1

    公开(公告)日：1995-12-21

    申请号：DE69023568

    申请日：1990-05-09

    Applicant: IBM

    Inventor： EMMA PHILIP GEORGE ,  KNIGHT JOSHUA WILSON ,  POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN

    IPC: G06F12/08

    Abstract: A cache memory system develops an optimum sequence for transferring data values between a main memory (50) and a line buffer (30) internal to the cache (20). At the end of a line transfer, the data in the line buffer (30) is written into the cache memory (20) as a block. Following an initial cache miss, the cache memory system monitors the sequence of data requests received for data in the line that is being read in from main memory (50). If the sequence being used to read in the data causes the processor (10) to wait for a specific data value in the line, a new sequence is generated in which the specific data value is read at an earlier time in the transfer cycle. This sequence is associated with the instruction that caused the first miss and is used for subsequent misses caused by the instruction. If, in the process of handling a first miss related to a specific instruction, a second miss occurs which is caused by the same instruction but which is for data in a different line of memory, the sequence associated with the instruction is marked as an ephemeral miss. Data transferred to the line buffer (30) in response to an ephemeral miss is not stored in the cache memory (20) and limited to that portion of the line accessed within the line buffer (30).

    Granting permissions for data access in a heterogeneous computing environment
    6.
    发明专利
    Granting permissions for data access in a heterogeneous computing environment 未知

    公开(公告)号：GB2496245A

    公开(公告)日：2013-05-08

    申请号：GB201216252

    申请日：2012-09-12

    Applicant: IBM

    Inventor： KREUZENSTEIN ROBERT KARL ,  YUDENFRIEND HARRY ,  KNIGHT JOSHUA WILSON ,  RUDDY ALAN JAMES ,  LEE JOHN ,  THOMPSON JOHN GLENN ,  CHAMBLISS DAVID DARDEN

    IPC: G06F21/62 ,  G06F3/06

    Abstract: A method of accessing data in a heterogeneous computing system, which may be operating in a mainframe arrangement, includes: receiving, in a first computing system 105 running a first operating system, a request from a second computing system 120 to access a data set 115, where the second computing system has a second operating system dissimilar to the first. The first system then prepares the data set for access by the second system, determines certain characteristics of the data set, passing them to the second system, and sets permissions for the second computing system to access the data set. This allows servers running operating systems that do not have access control mechanisms to use data that require such mechanisms to be used. The permissions may be rescinded following use of the data set.

    8.
    发明专利
    未知

    公开(公告)号：DE69023568T2

    公开(公告)日：1996-06-13

    申请号：DE69023568

    申请日：1990-05-09

    Applicant: IBM

    Inventor： EMMA PHILIP GEORGE ,  KNIGHT JOSHUA WILSON ,  POMERENE JAMES HERBERT ,  PUZAK THOMAS ROBERTS ,  RECHTSCHAFFEN RUDOLPH NATHAN

    IPC: G06F12/08

    Abstract: A cache memory system develops an optimum sequence for transferring data values between a main memory (50) and a line buffer (30) internal to the cache (20). At the end of a line transfer, the data in the line buffer (30) is written into the cache memory (20) as a block. Following an initial cache miss, the cache memory system monitors the sequence of data requests received for data in the line that is being read in from main memory (50). If the sequence being used to read in the data causes the processor (10) to wait for a specific data value in the line, a new sequence is generated in which the specific data value is read at an earlier time in the transfer cycle. This sequence is associated with the instruction that caused the first miss and is used for subsequent misses caused by the instruction. If, in the process of handling a first miss related to a specific instruction, a second miss occurs which is caused by the same instruction but which is for data in a different line of memory, the sequence associated with the instruction is marked as an ephemeral miss. Data transferred to the line buffer (30) in response to an ephemeral miss is not stored in the cache memory (20) and limited to that portion of the line accessed within the line buffer (30).

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