公开(公告)号：JP2006100479A

公开(公告)日：2006-04-13

申请号：JP2004283273

申请日：2004-09-29

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： CHOE KWANG SU ,  FOGEL KEITH ,  SADANA DEVENDRA K

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/265

Abstract: PROBLEM TO BE SOLVED: To provide a silicon-on-insulator (SOI) substrate structure and a manufacturing method thereof which are simple and cost-efficient.
SOLUTION: The method for manufacturing the SOI substrate structure is provided by oxidizing porous Si having a gradient. This porous Si having the gradient is formed by first implanting a (p-type or n-type) dopant into a substrate containing Si, activating this dopant using an activating annealing step, and then anodizing this implanted and activated dopant region in a solution containing HF. This Si having the gradient has a relatively coarse upper surface layer and a fine porous layer buried directly under this upper surface layer. According to the oxidation step, the fine buried porous layer is changed into a buried oxide layer, and the coarse upper surface layer is fused into a solid Si containing over-layer due to surface migration of Si atoms.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种简单且成本有效的绝缘体上硅（SOI）衬底结构及其制造方法。 解决方案：通过氧化具有梯度的多孔Si来提供SOI衬底结构的制造方法。 具有梯度的该多孔Si通过首先将（p型或n型）掺杂剂注入到含有Si的衬底中，使用活化退火步骤激活该掺杂剂，然后将该注入和活化的掺杂剂区域阳极氧化在含有 HF。 具有梯度的Si具有相对粗糙的上表面层和直接埋在该上表面层下方的细多孔层。 根据氧化步骤，由于Si原子的表面迁移，精细埋入多孔层变成掩埋氧化物层，粗糙的上表面层被熔融成为含有Si的固体Si层。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006041526A

公开(公告)日：2006-02-09

申请号：JP2005213971

申请日：2005-07-25

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： KEVIN K CHAN ,  DE SOUZA JOEL P ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L

IPC: H01L21/76 ,  H01L21/02 ,  H01L21/265 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

CPC classification number: H01L21/84 ,  H01L21/76243 ,  H01L21/76267 ,  H01L27/1203 ,  H01L27/1207

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a device on a crystal of orientation which brings about optimal performance by providing separation by an oxygen implantation (SIMOX) method for the formation of a flat hybrid orientation semiconductor on insulator (SOI) substrate having a crystal of different orientation. SOLUTION: A method comprises steps of: selecting a substrate having a lower semiconductor layer having first crystal orientation separated from an upper semiconductor layer having second crystal orientation by a thin insulating layer; replacing the upper semiconductor layer of a selected region with epitaxial growth semiconductor having the first crystal orientation; (i) forming a padding insulating region in an epitaxial growth semiconductor material and (ii) thickening an insulating layer under the upper semiconductor layer using ion implantation and annealing methods; and forming a hybrid orientation substrate in which two semiconductor materials of different crystal orientation have substantially identical thickness and are arranged on the common padding insulating layer. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种通过提供通过氧注入（SIMOX）方法分离以形成绝缘体上的平坦混合取向半导体（SOI）的方向来制造取向晶体的装置的方法，该方法产生最佳性能 ）衬底具有不同取向的晶体。 解决方案：一种方法包括以下步骤：通过薄绝缘层，选择具有从具有第二晶体取向的上半导体层分离的具有第一晶体取向的下半导体层的衬底; 用具有第一晶体取向的外延生长半导体代替所选区域的上半导体层; （i）在外延生长半导体材料中形成填充绝缘区域，和（ii）使用离子注入和退火方法使上半导体层下方的绝缘层增厚; 以及形成混合取向基板，其中两个不同晶体取向的半导体材料具有基本上相同的厚度并且布置在公共衬垫绝缘层上。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005026681A

公开(公告)日：2005-01-27

申请号：JP2004183839

申请日：2004-06-22

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  DOMENICUCCI ANTHONY G ,  FOGEL KEITH E ,  SADANA DEVENDRA K

IPC: H01L27/12 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762

CPC classification number: H01L21/7624 ,  Y10S438/933 ,  Y10T428/12674

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing an SiGe-on-insulator substrate material substantially relaxed, of high quality, and capable of being used as a template for strained-silicon. SOLUTION: The SOI substrate having an ultra-thin top Si layer is used as the template for compressive strain SiGe growth. When an SiGe layer is relaxed at an enough temperature, the property of its dislocation movement is such that strain release defect moves down into the thin Si layer when an embedded oxide shows semi-viscosity behavior. The thin Si layer is consumed by oxidation of an interface of the thin Si with the embedded oxide. This can be performed by using inner oxidation at a high temperature. Therefore, the role of the original thin Si layer is to use the inner oxidation and subsequently to act as a sacrificial defective sink capable of being consumed during an SiGe alloy being relaxed. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种制造绝缘体上绝缘体衬底材料的方法，其基本上是松弛的，高质量的，并且能够用作应变硅的模板。 解决方案：使用具有超薄顶部Si层的SOI衬底作为压缩应变SiGe生长的模板。 当SiGe层在足够的温度下松弛时，其位错运动的性质使得当嵌入的氧化物显示半粘度行为时，应变释放缺陷向下移动到薄的Si层中。 薄的Si层被薄的Si与嵌入的氧化物的界面的氧化所消耗。 这可以通过在高温下使用内部氧化来进行。 因此，原始薄Si层的作用是使用内部氧化，随后作为在SiGe合金松弛期间能够消耗的牺牲缺陷槽。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2009033196A

公开(公告)日：2009-02-12

申请号：JP2008258479

申请日：2008-10-03

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEPHEN W ,  FOGEL KEITH E ,  SADANA DEVENDRA K

IPC: H01L21/20 ,  H01L29/161 ,  H01L21/265 ,  H01L21/762

CPC classification number: H01L21/76243 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02664 ,  Y10S438/933

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming a relaxed SiGe-on-insulator substrate having improved relaxation, significantly lower defect density, and improved surface quality.
SOLUTION: The method includes a step for forming an SiGe alloy layer on a surface of a first single crystal Si layer. The first single crystal Si layer has an interface with an underlay barrier layer having resistance to Ge diffusion. Next, ions are implanted into the structure, the ions forming defects by which mechanical decoupling is achieved at the interface or vicinity of the interface; then a heating step is performed to the structure including the implanted ions, by which mutual diffusion of Ge through the first single crystal Si layer and SiGe layer is achieved; thereby a SiGe layer that is substantially relaxed single crystal and homogenous is formed on the barrier layer. A SiGe-on-insulator having improved properties and a heterostructure including it are also provided.
COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 解决的问题：提供一种形成松弛的绝缘体上硅衬底的方法，其具有改进的松弛，显着降低缺陷密度和改进的表面质量。 解决方案：该方法包括在第一单晶Si层的表面上形成SiGe合金层的步骤。 第一单晶Si层具有与Ge扩散性有抵抗性的底层阻挡层的界面。 接下来，将离子注入到结构中，离子形成缺陷，通过该缺陷在界面的界面或附近实现机械解耦; 然后对包括注入离子的结构进行加热步骤，由此实现Ge通过第一单晶Si层和SiGe层的相互扩散; 从而在阻挡层上形成基本上松弛的单晶并均匀的SiGe层。 还提供了具有改进性能的绝缘体上硅和包括其的异质结构。 版权所有（C）2009，JPO＆INPIT

公开(公告)号：JP2005079601A

公开(公告)日：2005-03-24

申请号：JP2004256027

申请日：2004-09-02

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K

IPC: H01L29/161 ,  C30B29/52 ,  C30B31/02 ,  H01L21/02 ,  H01L21/20 ,  H01L21/205 ,  H01L21/762 ,  H01L21/8238 ,  H01L27/12 ,  H01L29/04

CPC classification number: H01L21/7624 ,  C30B29/52 ,  C30B31/02 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02694 ,  Y10T428/24917

Abstract: PROBLEM TO BE SOLVED: To provide a manufacturing method for making a metastable strained SiGe layer. SOLUTION: The metastable SiGe layer is made by the method which includes a process that a layer containing Ge is formed on a surface of a layer disposed on a barrier layer to Ge diffusion containing Si in its upper surface portion thickness of 500 Å or less, and a process that a substantially metastable SiGe layer showing relaxation resistive property on the barrier layer is formed by heating the above-mentioned respective layers at the temperature enabling Ge to diffuse through the layer containing Si in its upper surface portion and the layer containing Ge mutually. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种制造亚稳态应变SiGe层的制造方法。 解决方案：亚稳态SiGe层是通过以下方法制成的，该方法包括：在设置在阻挡层上的层的表面上形成含有Ge的层，其上表面部分厚度为含有Si的Ge扩散 并且通过在使Ge能够通过其上表面部分中含有Si的层扩散的温度下加热上述各层来形成在阻挡层上显示松弛电阻性质的基本上亚稳态的SiGe层的工艺， 包含Ge相互。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2000243944A

公开(公告)日：2000-09-08

申请号：JP2000035433

申请日：2000-02-14

Applicant: IBM

Inventor： LEOBANDUNG EFFENDI ,  SADANA DEVENDRA K ,  SCHEPIS DOMINIC J ,  SHAHIDI GHAVAM

IPC: H01L21/205 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide a planar silicon-on-insulator(SOI) structure and a method for manufacturing the structure. SOLUTION: The SOI structure has a silicon wafer 10, an oxide layer 12 and a silicon layer 14. A trench is formed as extended from an upper surface of the structure to the silicon wafer, and the trench is filled with semiconductor 34. The trench has an upper part, a bottom surface and a sidewall. The sidewall has a sidewall silicon part. The sidewall silicon part of the trench sidewall is covered with a trench sidewall oxide layer 30. A protective sidewall 32 is formed on the trench sidewall and a trench sidewall oxide layer as extended from the upper part of the trench to the bottom surface of the trench.

公开(公告)号：WO2007149581A2

公开(公告)日：2007-12-27

申请号：PCT/US2007014684

申请日：2007-06-25

Applicant: IBM ,  KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

Inventor： KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

IPC: H01L21/336 ,  H01L29/778

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A semiconductor-containing heterostructure including, from bottom to top, a IH-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a HI-V compound semiconductor barrier layer, and an optional, yet preferred, IH-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The HI-V compound semiconductor buffer layer and the HI-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the pi-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

Abstract translation: 含半导体的异质结构包括从下至上的IH-V化合物半导体缓冲层，III-V族化合物半导体沟道层，HI-V族化合物半导体阻挡层和任选的，但优选的IH-V化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 HI-V化合物半导体缓冲层和HI-V化合物半导体阻挡层由具有比p-V化合物半导体沟道层的带隙更宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，所以载流子在特定栅极偏置范围内被限制在沟道层。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。

公开(公告)号：WO2004109776A3

公开(公告)日：2005-05-19

申请号：PCT/US2004016903

申请日：2004-05-28

Applicant: IBM ,  BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH E ,  SADANA DEVENDRA K

IPC: H01L21/20 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L21/7624 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02664 ,  Y10T428/12674

Abstract: The present invention provides a method of fabricating a SiGe-on-insulator substrate in which lattice engineering is employed to decouple the interdependence between SiGe thickness, Ge fraction and strain relaxation. The method includes providing a SiGe-on-insulator substrate material comprising a SiGe alloy layer having a selected in-plane lattice parameter, a selected thickness parameter and a selected Ge content parameter, wherein the selected in-plane lattice parameter has a constant value and one or both of the other parameters, i.e., thickness or Ge content, have adjustable values; and adjusting one or both of the other parameters to final selected values, while maintaining the selected in-plane lattice parameter. The adjusting is achieved utilizing either a thinning process or a thermal dilution process depending on which parameters are fixed and which are adjustable.

Abstract translation: 本发明提供了一种制造绝缘体上硅衬底的方法，其中使用晶格工程来去耦合SiGe厚度，Ge分数和应变松弛之间的相互依赖性。 该方法包括提供一种绝缘体上硅衬底材料，其包括具有选定的面内晶格参数的SiGe合金层，选定的厚度参数和所选择的Ge含量参数，其中所选择的面内晶格参数具有恒定值， 一个或两个其他参数，即厚度或Ge含量，具有可调整的值; 并且在保持所选择的平面内晶格参数的同时将其他参数中的一个或两个调整为最终选择的值。 根据哪些参数是固定的，哪些是可调节的，利用稀化过程或热稀释过程实现调节。

公开(公告)号：JP2006191029A

公开(公告)日：2006-07-20

申请号：JP2005363874

申请日：2005-12-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DE SOUZA JOEL P ,  OTT JOHN A ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L

IPC: H01L21/02

CPC classification number: H01L21/187 ,  H01L21/76251

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a bonding interface between Si having characteristics equal to that attained by hydrophobic bonding by removing an ultra thin interface oxide remaining after hydrophobic wafer bonding between Si.
SOLUTION: The interface oxide layer in the order of about 2-3 nm is dissolved and removed by, for example, high temperature annealing at 1,300-1,330°C only for 1-5 hours. The invention is most effectively used if the Si surface of a bonding interface has a different surface orientation as, for example, the Si surface with (100) orientation is bonded to the Si surface with (110) orientation. In more generous modes of this invention, an undesired material arranged on the bonding interface of two silicon-contained semiconductor materials can be removed by a similar annealing process. The surface crystal orientation, fine structure (single crystal, polycrystal, or amorphous), and elements of two silicon-contained semiconductor materials may or may not be identical.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供通过除去Si之间的疏水性晶片接合之后残留的超薄界面氧化物，形成具有与通过疏水接合获得的特性相同的特性的Si之间的结合界面的方法。 解决方案：通过例如1300-133℃的高温退火将约2-3nm量级的界面氧化物层溶解并除去1-5小时。 如果接合界面的Si表面具有不同的表面取向，则本发明是最有效的，因为例如具有（110）取向的具有（100）取向的Si表面结合到Si表面。 在本发明的更宽泛的模式中，可以通过类似的退火工艺去除布置在两个含硅半导体材料的结合界面上的不需要的材料。 表面晶体取向，精细结构（单晶，多晶或非晶）和两个含硅半导体材料的元素可以相同也可以不相同。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2006191028A

公开(公告)日：2006-07-20

申请号：JP2005363826

申请日：2005-12-16

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation

Inventor： DE SOUZA JOEL P ,  FOGEL KEITH E ,  OTT JOHN ALBRECHT ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L

IPC: H01L21/20 ,  H01L21/324

CPC classification number: H01L21/26506 ,  H01L21/2022

Abstract: PROBLEM TO BE SOLVED: To provide a method for amorphization/template re-crystallization for changing orientation in the selected region of a silicon, without remaining defect of high density, by preparing an anneal process optimized to remove defects caused by damage due to injection, in a single crystal silicon. SOLUTION: The region of Si having a first crystal orientation is amorphised by iron-implantation, and is re-crystallized into the orientation of a template layer having different orientation, in an amorphising/template re-crystallization (ATR) process. A reoriented Si of low defective density in the process is formed by this method. More specifically, the invention relates to a high temperature annealing condition required for eliminating defects remaining in an Si-contained single crystal semiconductor material formed of the layer whose orientation is identical or different from the original orientation of amorphous layer by amorphising caused by ion-implantation and template re-crystallization. The main factor of that is a thermal process for removing defects remaining after initial re-crystallization annealing, in the temperature range of 1,250-1,330°C for several minutes to several hours. A reoriented Si of low defective density, formed by ATR, is provided as well for use with a hybrid orientation substrate. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供一种用于改变所选择的硅区域中的取向的无定形/模板再结晶的方法，而不存在高密度的缺陷，通过制备优化的消除由于损坏引起的缺陷的退火工艺 注入单晶硅。 解决方案：通过铁注入将具有第一晶体取向的Si区域非晶化，并且在非晶化/模板再结晶（ATR）工艺中，重新结晶成具有不同取向的模板层的取向。 通过该方法形成该方法中的低缺陷密度的重新取向的Si。 更具体地说，本发明涉及一种高温退火条件，用于消除由该离子注入引起的非晶形取向与非晶层的原始取向相同或不同的Si形成的含Si单晶半导体材料残留的缺陷 和模板再结晶。 其主要因素是在初始再结晶退火后，在1,250-133℃的温度范围内去除几分钟至数小时的缺陷的热处理。 还提供了由ATR形成的低缺陷密度的重新取向的Si，以及与混合取向基板一起使用。 版权所有（C）2006，JPO＆NCIPI