公开(公告)号：EP1532659A4

公开(公告)日：2005-12-14

申请号：EP03736783

申请日：2003-06-03

Applicant: IBM

Inventor： FRIED DAVID M ,  NOWAK EDWARD J ,  RAINEY BETH ANN ,  SADANA DEVENDRA K

IPC: H01L27/088 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/8238 ,  H01L29/78 ,  H01L29/786 ,  H01L21/00

CPC classification number: H01L29/7851 ,  H01L21/823828 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7853

Abstract: The present invention thus provides a device structure and method for forming fin (210) Field Effect Transistors (FETs) from bulk semiconductor wafers (200) while providing improved wafer to wafer device uniformity. Specifically, the invention provides a height control layer (212), such as a damaged portion of the substrate (200) or a marker layer, which provides uniformity of fin height. Additionally, the invention provides provides isolation (214) between fins (210) which also provides for optimization and narrowing of fin width by selective oxidation of a portion (212) of the substrate relative to an oxidized portion (216) of the fin sidewalk. The device structure and methods of the present invention thus provide the advantages of uniform finFET fabrication while using cost effect bulk wafers.

公开(公告)号：EP1790003A4

公开(公告)日：2011-01-12

申请号：EP05784302

申请日：2005-08-04

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  CHEN HUAJIE ,  FOGEL KEITH ,  MITCHELL RYAN M ,  SADANA DEVENDRA K

IPC: H01L21/36 ,  H01L21/02 ,  H01L21/20 ,  H01L31/117

CPC classification number: H01L29/1054 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02507 ,  H01L21/02532

公开(公告)号：EP1479103A4

公开(公告)日：2005-02-09

申请号：EP03731957

申请日：2003-01-16

Applicant: IBM

Inventor： BEDELL STEPHEN W ,  CHU JACK O ,  FOGEL KEITH E ,  KOESTER STEPHEN J ,  SADANA DEVENDRA K ,  OTT JOHN ALBRECHT

IPC: H01L27/08 ,  H01L21/02 ,  H01L21/20 ,  H01L21/225 ,  H01L21/324 ,  H01L21/337 ,  H01L21/762 ,  H01L27/12 ,  H01L29/786 ,  H01L21/331

CPC classification number: H01L21/76243 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/02612 ,  H01L21/2251 ,  H01L21/324 ,  H01L27/1203 ,  H01L29/66916 ,  Y10S438/938 ,  Y10T428/12674 ,  Y10T428/265 ,  Y10T428/31848

Abstract: A method of forming a thin, high-quality relaxed SiGe-on-insulator substrate (10) material is provided which first includes forming a SiGe or pure Ge layer on a surface of a first single crystal Si layer (14) which is present atop a barrier layer (12) that is resistant to the diffusion of Ge. Optionally forming a Si cap layer (18) over the SiGe or pure Ge layer (16), and thereafter heating the various layers at a temperature which permits interdiffusion of Ge throughtout the first single crystal Si layer (14), the optional Si cap (18) and the SiGe or pure Ge layer (16) thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer (12). Additional SiGe regrowth and/or formation of a strained epi-Si layer may follow the above steps. SiGe-on-insulator substrate materials as well as structures including at least the SiGe-on-insulator substrate material are also disclosed herein.

Abstract translation: 提供了一种形成薄的，高品质的弛豫SiGe绝缘体上的基板材料的方法，其首先包括形成第一单晶Si层的表面上的SiGe或纯Ge层，其存在的顶上即耐阻挡层 到Ge的扩散。 OPTIONALLY形成在SiGe或纯Ge层中的Si间隙层，并随后在其允许的Ge的相互扩散在整个第一单晶Si层的温度下加热的各种层，任选的Si盖和SiGe或纯Ge层，从而形成 基本松弛，单晶SiGe层在阻挡层上。 额外的SiGe再生长和/或形成的应变外延Si层的可遵循上述步骤。 上SiGe绝缘体基板材料以及包含结构至少在SiGe绝缘体上的基板材料，因此是在盘游离缺失。

公开(公告)号：EP2588650A4

公开(公告)日：2014-03-19

申请号：EP11801264

申请日：2011-06-23

Applicant: MATHESON TRI GAS INC ,  IBM

Inventor： FRANCIS TERRY ARTHUR ,  HASAKA SATOSHI ,  BRABANT PAUL DAVID ,  TORRES ROBERT JR ,  HE HONG ,  REZNICEK ALEXANDER ,  ADAM THOMAS N ,  SADANA DEVENDRA K

IPC: C30B25/02 ,  C23C16/30 ,  C23C16/32 ,  C30B29/06 ,  H01L21/02

CPC classification number: H01L21/02532 ,  C23C16/30 ,  C23C16/325 ,  C30B25/02 ,  C30B29/06 ,  H01L21/0237 ,  H01L21/02529 ,  H01L21/02573 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636

公开(公告)号：EP1709671A4

公开(公告)日：2010-06-16

申请号：EP04703076

申请日：2004-01-16

Applicant: IBM

Inventor： CHEN HUAJIE ,  BEDELL STEPHEN W ,  SADANA DEVENDRA K ,  MOCUTA DAN M

IPC: H01L21/331 ,  H01L21/20 ,  H01L21/205 ,  H01L21/316 ,  H01L21/762 ,  H01L21/84 ,  H01L29/10 ,  H01L29/786

CPC classification number: H01L21/76256 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02664 ,  H01L21/31658 ,  H01L21/84 ,  H01L29/1054 ,  H01L29/78687

公开(公告)号：EP1875508A4

公开(公告)日：2009-08-05

申请号：EP06750977

申请日：2006-04-21

Applicant: IBM

Inventor： DESOUZA JOEL P ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SUNG CHUN-YUNG ,  YANG MIN ,  YIN HAIZHOU

IPC: H01L29/04

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/7624 ,  H01L21/823807 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0922 ,  H01L27/1203 ,  H01L29/045 ,  H01L29/66636 ,  H01L29/7833

Abstract: Hybrid orientation substrates allow the fabrication of complementary metal oxide semiconductor (CMOS) circuits in which the n-type field effect transistors (nFETs) are disposed in a semiconductor orientation which is optimal for electron mobility and the p-type field effect transistors (pFETs) are disposed in a semiconductor orientation which is optimal for hole mobility. This invention discloses that the performance advantages of FETs formed entirely in the optimal semiconductor orientation may be achieved by only requiring that the device's channel be disposed in a semiconductor with the optimal orientation. A variety of new FET structures are described, all with the characteristic that at least some part of the FET's channel has a different orientation than at least some part of the FET's source and/or drain. Hybrid substrates into which these new FETs might be incorporated are described along with their methods of making.

公开(公告)号：WO2005031810A3

公开(公告)日：2005-06-23

申请号：PCT/US2004029378

申请日：2004-09-10

Applicant: IBM ,  BEDELL STEPHEN W ,  CHOE KWANG SU ,  FOGEL KEITH F ,  SADANA DEVENDRA K

Inventor： BEDELL STEPHEN W ,  CHOE KWANG SU ,  FOGEL KEITH F ,  SADANA DEVENDRA K

IPC: C22F1/10 ,  H01L21/20 ,  H01L21/762

CPC classification number: H01L21/76227 ,  C22F1/10 ,  H01L21/02378 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02532 ,  H01L21/02667 ,  H01L21/76245 ,  H01L29/78603

Abstract: A simple and direct method of forming a SiGe-on-insulator that relies on the oxidation of a porous silicon layer (or region) that is created beneath a Ge-containing layer is provided. The method includes the steps of providing a structure comprising a Si-containing substrate having a hole-rich region formed therein and a Ge-containing layer atop the Si-containing substrate; converting the hole-rich region into a porous region; and annealing the structure including the porous region to provide a substantially relaxed SiGe-on-insulator material.

Abstract translation: 提供一种形成依赖于在含Ge层下形成的多孔硅层（或区域）的氧化的绝缘体上硅的简单且直接的方法。 该方法包括以下步骤：提供包括其中形成有富空穴的含Si衬底和含Si衬底顶部的含Ge层的结构; 将富含孔的区域转化为多孔区域; 并退火包括多孔区域的结构，以提供基本上松弛的绝缘体上的SiGe。

公开(公告)号：WO2007130333A2

公开(公告)日：2007-11-15

申请号：PCT/US2007010411

申请日：2007-04-30

Applicant: IBM ,  BEDELL STEPHEN W ,  DESOUZA JOEL P ,  REN ZHIBIN ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SHAHIDI GHAVAM

Inventor： BEDELL STEPHEN W ,  DESOUZA JOEL P ,  REN ZHIBIN ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SHAHIDI GHAVAM

IPC: H01L21/8234

CPC classification number: H01L29/66628 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  Y10S438/909 ,  Y10S438/943

Abstract: This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (SfD) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined withex situ heat treatments in a "divided-dose-anneal-in-between" (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

Abstract translation: 本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（在绝缘体上的超薄硅层中的FET中的源/漏（SfD）区域的潜在问题）和植入物 诱导的应变S / D区域的塑性弛豫（对于通道应变由嵌入的S / D区域与下面的基底层不匹配而提供的应变通道FET的潜在问题）。 在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。 在第二实施例中，离子注入在“分剂量退火中间”（DDAB）方案中组合了原位热处理，避免了对能够进行热植入的加工的需要。

公开(公告)号：JP2003309254A

公开(公告)日：2003-10-31

申请号：JP2003103083

申请日：2003-04-07

Applicant: Internatl Business Mach Corp ,  インターナショナル・ビジネス・マシーンズ・コーポレーション

Inventor： HOVEL HAROLD J ,  NORCOTT MAURICE H ,  SADANA DEVENDRA K

IPC: H01L21/265 ,  H01L21/02 ,  H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76243

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing a high-quality silicon-on- insulator (SOI) substrate material having a buried oxide (BOX) region whose thickness is about 300 nm or less.
SOLUTION: In this method, a high quality SOI substrate is formed by using a plurality of implants and a plurality of annealing steps. Particularly, this method includes at least a first oxygen ion implant wherein a primary oxide seed region is formed, a first annealing step, a second oxygen ion implant wherein a BOX adjustment oxide seed region is formed, and a second annealing step. In the annealing step, the seed region is converted into an embedded oxide region.
COPYRIGHT: (C)2004,JPO

Abstract translation: 要解决的问题：提供一种制造具有厚度为约300nm以下的掩埋氧化物（BOX）区域的高品质绝缘硅（SOI）衬底材料的方法。 解决方案：在该方法中，通过使用多个注入和多个退火步骤形成高质量的SOI衬底。 特别地，该方法至少包括其中形成主氧化物种子区域的第一氧离子注入，第一退火步骤，其中形成BOX调整氧化物种子区域的第二氧离子注入和第二退火步骤。 在退火步骤中，种子区域被转换为嵌入的氧化物区域。 版权所有（C）2004，JPO

公开(公告)号：JP2002324905A

公开(公告)日：2002-11-08

申请号：JP2002067509

申请日：2002-03-12

Applicant: IBM

Inventor： IYER SUNDAR K ,  SADANA DEVENDRA K

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/74 ,  H01L21/76 ,  H01L21/762 ,  H01L21/8238 ,  H01L23/52 ,  H01L27/08 ,  H01L27/092 ,  H01L27/12 ,  H01L29/786

Abstract: PROBLEM TO BE SOLVED: To provide a method of forming a transistor body contact in an SOI device. SOLUTION: An SOI substrate contact is provided on the bodies of transistors fabricated in an SOI silicon wafer by selectively making an insulating layer below the bodies leaky. This is achieved by implanting, below a set of transistor body locations, a predetermined dose of ions having an energy such that the implanted region extends vertically through a buried insulator between the body and the wafer substrate. Thereafter, a sufficient voltage is applied to break down an oxide, and a conductive path is made between the body and the substrate.