公开(公告)号：WO2005043614A3

公开(公告)日：2005-11-03

申请号：PCT/EP2004052704

申请日：2004-10-28

Applicant: IBM ,  IBM UK ,  CHEN TZE-CHIANG ,  COHEN GUY ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA ,  SHAHIDI GHAVAM

Inventor： CHEN TZE-CHIANG ,  COHEN GUY ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA ,  SHAHIDI GHAVAM

IPC: H01L21/762 ,  H01L27/12 ,  H01L27/144 ,  H01L31/0232 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/105 ,  H01L31/18 ,  H01L21/265 ,  H01L21/306 ,  H01L21/324 ,  H01L27/14

CPC classification number: H01L21/76254 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/1812 ,  Y02E10/547

Abstract: A method for fabricating germanium-on-insulator (GOI) substrate materials, the GOI substrate materials produced by the method and various structures that can include at least the GOI substrate materials of the present invention are provided. The GOI substrate material include at least a substrate, a buried insulator layer located atop the substrate, and a Ge-containing layer, preferably pure Ge, located atop the buried insulator layer. In the GOI substrate materials of the present invention, the Ge-containing layer may also be referred to as the GOI film. The GOI film is the layer of the inventive substrate material in which devices can be formed.

Abstract translation: 提供了用于制造绝缘体上锗（GOI）衬底材料的方法，通过该方法制造的GOI衬底材料以及可以包括至少本发明的GOI衬底材料的各种结构。 GOI衬底材料至少包括衬底，位于衬底顶上的掩埋绝缘体层以及位于掩埋绝缘体层顶上的含Ge层，优选纯Ge。 在本发明的GOI基板材料中，含Ge层也可以被称为GOI膜。 GOI膜是其中可以形成器件的本发明衬底材料的层。

公开(公告)号：JP2000243944A

公开(公告)日：2000-09-08

申请号：JP2000035433

申请日：2000-02-14

Applicant: IBM

Inventor： LEOBANDUNG EFFENDI ,  SADANA DEVENDRA K ,  SCHEPIS DOMINIC J ,  SHAHIDI GHAVAM

IPC: H01L21/205 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12

Abstract: PROBLEM TO BE SOLVED: To provide a planar silicon-on-insulator(SOI) structure and a method for manufacturing the structure. SOLUTION: The SOI structure has a silicon wafer 10, an oxide layer 12 and a silicon layer 14. A trench is formed as extended from an upper surface of the structure to the silicon wafer, and the trench is filled with semiconductor 34. The trench has an upper part, a bottom surface and a sidewall. The sidewall has a sidewall silicon part. The sidewall silicon part of the trench sidewall is covered with a trench sidewall oxide layer 30. A protective sidewall 32 is formed on the trench sidewall and a trench sidewall oxide layer as extended from the upper part of the trench to the bottom surface of the trench.

公开(公告)号：WO2007149581A3

公开(公告)日：2008-08-28

申请号：PCT/US2007014684

申请日：2007-06-25

Applicant: IBM ,  KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

Inventor： KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

IPC: H01L21/336

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A semiconductor-containing heterostructure including, from bottom to top, a IH-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a HI-V compound semiconductor barrier layer, and an optional, yet preferred, IH-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The HI-V compound semiconductor buffer layer and the HI-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the pi-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

Abstract translation: 一种含半导体的异质结构，包括从底部到顶部的IH-V化合物半导体缓冲层，III-V族化合物半导体沟道层，HI-V族化合物半导体阻挡层和任选的，但优选的IH-V化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 HI-V化合物半导体缓冲层和HI-V化合物半导体阻挡层由具有比p-V化合物半导体沟道层的带隙更宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，载流子在特定栅极偏置范围内被限制在沟道层上。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。

公开(公告)号：WO2007149581A2

公开(公告)日：2007-12-27

申请号：PCT/US2007014684

申请日：2007-06-25

Applicant: IBM ,  KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

Inventor： KIEWRA EDWARD W ,  KOESTER STEVEN J ,  SADANA DEVENDRA K ,  SHAHIDI GHAVAM ,  SUN YANNING

IPC: H01L21/336 ,  H01L29/778

CPC classification number: H01L29/7787 ,  H01L29/66462

Abstract: A semiconductor-containing heterostructure including, from bottom to top, a IH-V compound semiconductor buffer layer, a III-V compound semiconductor channel layer, a HI-V compound semiconductor barrier layer, and an optional, yet preferred, IH-V compound semiconductor cap layer is provided. The barrier layer may be doped, or preferably undoped. The HI-V compound semiconductor buffer layer and the HI-V compound semiconductor barrier layer are comprised of materials that have a wider band gap than that of the pi-V compound semiconductor channel layer. Since wide band gap materials are used for the buffer and barrier layer and a narrow band gap material is used for the channel layer, carriers are confined to the channel layer under certain gate bias range. The inventive heterostructure can be employed as a buried channel structure in a field effect transistor.

Abstract translation: 含半导体的异质结构包括从下至上的IH-V化合物半导体缓冲层，III-V族化合物半导体沟道层，HI-V族化合物半导体阻挡层和任选的，但优选的IH-V化合物 提供半导体盖层。 阻挡层可以是掺杂的，或者优选地是未掺杂的。 HI-V化合物半导体缓冲层和HI-V化合物半导体阻挡层由具有比p-V化合物半导体沟道层的带隙更宽的带隙的材料构成。 由于宽带隙材料用于缓冲层和阻挡层，并且窄带隙材料用于沟道层，所以载流子在特定栅极偏置范围内被限制在沟道层。 本发明的异质结构可以用作场效应晶体管中的掩埋沟道结构。

公开(公告)号：WO2007130333A2

公开(公告)日：2007-11-15

申请号：PCT/US2007010411

申请日：2007-04-30

Applicant: IBM ,  BEDELL STEPHEN W ,  DESOUZA JOEL P ,  REN ZHIBIN ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SHAHIDI GHAVAM

Inventor： BEDELL STEPHEN W ,  DESOUZA JOEL P ,  REN ZHIBIN ,  REZNICEK ALEXANDER ,  SADANA DEVENDRA K ,  SAENGER KATHERINE L ,  SHAHIDI GHAVAM

IPC: H01L21/8234

CPC classification number: H01L29/66628 ,  H01L21/26513 ,  H01L21/324 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/7848 ,  H01L29/78618 ,  H01L29/78684 ,  Y10S438/909 ,  Y10S438/943

Abstract: This invention teaches methods of combining ion implantation steps with in situ or ex situ heat treatments to avoid and/or minimize implant-induced amorphization (a potential problem for source/drain (SfD) regions in FETs in ultrathin silicon on insulator layers) and implant-induced plastic relaxation of strained S/D regions (a potential problem for strained channel FETs in which the channel strain is provided by embedded S/D regions lattice mismatched with an underlying substrate layer). In a first embodiment, ion implantation is combined with in situ heat treatment by performing the ion implantation at elevated temperature. In a second embodiment, ion implantation is combined withex situ heat treatments in a "divided-dose-anneal-in-between" (DDAB) scheme that avoids the need for tooling capable of performing hot implants.

Abstract translation: 本发明教导了将离子注入步骤与原位或非原位热处理组合以避免和/或最小化植入物诱导的非晶化（在绝缘体上的超薄硅层中的FET中的源/漏（SfD）区域的潜在问题）和植入物 诱导的应变S / D区域的塑性弛豫（对于通道应变由嵌入的S / D区域与下面的基底层不匹配而提供的应变通道FET的潜在问题）。 在第一实施例中，通过在升高的温度下进行离子注入将离子注入与原位热处理组合。 在第二实施例中，离子注入在“分剂量退火中间”（DDAB）方案中组合了原位热处理，避免了对能够进行热植入的加工的需要。

公开(公告)号：WO2011037743A3

公开(公告)日：2011-07-07

申请号：PCT/US2010048039

申请日：2010-09-08

Applicant: IBM ,  CHENG KANGGUO ,  KHAKIFIROOZ ALI ,  DORIS BRUCE B ,  SHAHIDI GHAVAM

Inventor： CHENG KANGGUO ,  KHAKIFIROOZ ALI ,  DORIS BRUCE B ,  SHAHIDI GHAVAM

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7848 ,  H01L21/2257 ,  H01L21/26586 ,  H01L29/165 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7834

Abstract: A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack (18), e.g., FET, located on an upper surface (14) of a semiconductor substrate (12). The structure further includes a first epitaxy semiconductor material (34) that induces a strain upon a channel (40) of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions (28) in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region (38) is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material (36) located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.

Abstract translation: 提供了高性能半导体结构和制造这种结构的方法。 半导体结构包括位于半导体衬底（12）的上表面（14）上的至少一个栅叠层（18），例如FET。 该结构还包括在至少一个栅极堆叠的沟道（40）上引起应变的第一外延半导体材料（34）。 所述第一外延半导体材料位于所述至少一个栅极堆叠的基准面上，基本上位于所述衬底中的存在于所述至少一个栅极叠层的相对侧上的一对凹陷区域（28）内。 扩散延伸区域（38）位于每个凹陷区域中的所述第一外延半导体材料的上表面内。 该结构还包括位于扩散延伸区域的上表面上的第二外延半导体材料（36）。 第二外延半导体材料具有比第一外延半导体材料更高的掺杂剂浓度。

公开(公告)号：DE10003014B4

公开(公告)日：2005-06-23

申请号：DE10003014

申请日：2000-01-25

Applicant: IBM

Inventor： LEOBANDUNG EFFENDI ,  SADANA DEVENDRA K ,  SCHEPIS DOMINIC J ,  SHAHIDI GHAVAM

IPC: H01L21/205 ,  H01L21/76 ,  H01L21/762 ,  H01L27/12 ,  H01L21/84

Abstract: A planar silicon-on-insulator (SOI) structure and a process for fabricating the structure. The SOI structure has a silicon wafer, an oxide layer, and a silicon layer. Trenches are formed, extending from the top surface of the structure to the silicon wafer, and are filled with a semiconductor. The trenches have a top, a bottom, and side walls. The side walls have side-wall silicon portions. The side-wall silicon portions of the trench side walls are covered by trench side-wall oxide layers. A protective side wall extends over the trench side walls and trench side-wall oxide layers from the trench top to the trench bottom.

公开(公告)号：DE112012005166T5

公开(公告)日：2014-08-28

申请号：DE112012005166

申请日：2012-09-13

Applicant: IBM

Inventor： CHENG KANGGUO ,  DORIS BRUCE B ,  KHAKIFIROOZ ALI ,  SHAHIDI GHAVAM

IPC: H01L27/06 ,  H01L29/78 ,  H01L29/93

Abstract: Ein ETSOI-Transistor und ein Kondensator werden in einer Transistor- bzw. einer Kondensatorzone durch Ätzen durch eine ETSOI-Schicht und eine dünne BOX-Schicht in einem Ersatz-Gate-HK/MG-Ablauf gebildet. Die Bildung des Kondensators ist mit einem ETSOI-Ersatz-Gate-CMOS-Ablauf kompatibel. Eine Kondensatorelektrode mit niedrigem Widerstand macht es möglich, einen Kondensator oder Varaktor hoher Qualität zu erhalten. Das Fehlen einer Topographie während des Strukturierens des Platzhalter-Gates wird durch Lithographie in Kombination mit einem geeigneten Ätzen ermöglicht.

公开(公告)号：GB2510544A

公开(公告)日：2014-08-06

申请号：GB201410069

申请日：2012-09-13

Applicant: IBM

Inventor： CHENG KANGGUO ,  DORIS BRUCE ,  KHAKIFIROOZ ALI ,  SHAHIDI GHAVAM

IPC: H01L29/94 ,  H01L27/12

Abstract: An ETSOI transistor and a capacitor are formed respectively in a transistor and capacitor region thereof by etching through an ETSOI and thin BOX layers in a replacement gate HK/MG flow. The capacitor formation is compatible with an ETSOI replacement gate CMOS flow. A low resistance capacitor electrode makes it possible to obtain a high quality capacitor or varactor. The lack of topography during dummy gate patterning are achieved by lithography in combination accompanied with appropriate etch.

公开(公告)号：DE102013211231B4

公开(公告)日：2016-05-12

申请号：DE102013211231

申请日：2013-06-17

Applicant: IBM

Inventor： HEKMATSHOARTABARI BAHMAN ,  KHAKIFIROOZ ALI ,  SHAHIDI GHAVAM ,  SHAHRJERDI DAVOOD

IPC: H01L31/18 ,  H01L31/0236 ,  H01L31/0687 ,  H01L31/0725

Abstract: Verfahren zum Bilden einer Tandem-Fotovoltaikeinheit, wobei das Verfahren aufweist: Bereitstellen (102) von massivem Germanium oder einer auf einem Siliciumsubstrat gebildeten Germaniumschicht; Nassätzen der Germaniumschicht unter Verwendung eines sauren Ätzmittels, das Phosphorsäure, Wasserstoffperoxid und Ethanol in einem Verhältnis von 1:1:1 enthält; Bilden pyramidenartiger Formen (106; 108) in der Germaniumschicht derart, dass (111)-Kristallflächen (104) freigelegt werden, um eine texturierte Oberfläche zu bilden; Dotieren einer oberen Oberfläche (110) der Germaniumschicht, um einen ersten p-n-Übergang auf oder oberhalb der texturierten Oberfläche zu bilden; Abscheiden einer ersten Halbleiterschicht (112), die der texturierten Oberfläche folgt, auf der oberen Oberfläche, wobei die erste Halbleiterschicht eine GaAs-Schicht oder Legierungen daraus enthält; Dotieren eines Teils der ersten Halbleiterschicht, um einen zweiten p-n-Übergang (132) zu bilden; Abscheiden einer zweiten Halbleiterschicht (116), die dem Profil der texturierten Oberfläche folgt, auf der ersten Halbleiterschicht, wobei die zweite Halbleiterschicht eine GaP-Schicht oder Legierungen daraus enthält; und Dotieren eines Teils der zweiten Halbleiterschicht, um einen dritten p-n-Übergang (134) zu bilden.