公开(公告)号：AU2015238663B2

公开(公告)日：2017-05-25

申请号：AU2015238663

申请日：2015-03-16

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY JR CHARLES

IPC: G06F9/46

Abstract: THREAD CONTEXT RESTORATION IN A MULTITHREADING COMPUTER SYSTEM Amultithreading computer system includesa configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method including disabling one or more secondary threads based on switching from MT mode to ST mode. A thread context of secondary threads is made unavailable to programs. Based on a last-set program-specified maximum thread-id indicating MT, the thread context is obtained by a) executing a set MT instruction to resume the MT mode, and b) based on being in the resumed MT mode, accessing the thread context.

公开(公告)号：HUE029040T2

公开(公告)日：2017-01-30

申请号：HUE12866318

申请日：2012-11-13

Applicant: IBM

Inventor： GAINEY CHARLES JR ,  KUBALA JEFFREY PAUL ,  FARRELL MARK ,  SCHMIDT DONALD WILLIAM ,  MULDER JAMES ,  PIERCE BERNARD ,  ROGERS ROBERT

IPC: G06F9/46 ,  G06F9/54 ,  G06F11/14

公开(公告)号：DE112015000203T5

公开(公告)日：2016-09-01

申请号：DE112015000203

申请日：2015-02-23

Applicant: IBM

Inventor： GREINER DAN ,  SLEGEL TIMOTHY ,  JACOBI CHRISTIAN ,  SCHMIDT DONALD WILLIAM ,  MITRAN MARCEL ,  GAINEY CHARLES JR

IPC: G06F9/52 ,  G06F9/30 ,  G06F9/38 ,  G06F9/455

Abstract: Bereitgestellt wird eine Verzögerungseinrichtung, in der eine Programmausführung verzögert werden kann, bis ein vordefiniertes Ereignis eintritt, z. B. bis ein Vergleich von Arbeitsspeicherpositionen eine wahre Bedingung ergibt, eine Zeitüberschreitung erreicht wird, eine Unterbrechung ausgesetzt wird oder eine andere Bedingung gegeben ist. Die Verzögerungseinrichtung beinhaltet einen oder mehrere „Compare and Delay”-Maschinenbefehle, mit denen eine Ausführung verzögert wird. Der eine oder die mehreren „Compare and Delay”-Befehle können einen 32-Bit-„Compare and Delay”-Befehl (CAD-Befehl) und einen 64-Bit-„Compare and Delay”-Befehl (CADG-Befehl) beinhalten.

公开(公告)号：AU2015238632A1

公开(公告)日：2016-08-04

申请号：AU2015238632

申请日：2015-03-19

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY JR CHARLES ,  JACOBI CHRISTIAN

IPC: G06F9/50 ,  G06F9/38

Abstract: Embodiments relate to dynamic enablement of multithreading. According to an aspect, a computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread, and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. The computer system also includes a multithreading facility configured to control the configuration to perform a method. The method includes executing in the primary thread in the ST mode, an MT mode setting instruction. A number of threads requested is obtained from a location specified by the MT mode setting instruction. Based on determining that the number of threads requested indicates multiple threads, the MT mode is enabled to execute the multiple threads including the primary thread and the one or more secondary threads.

公开(公告)号：CA2940990A1

公开(公告)日：2015-10-01

申请号：CA2940990

申请日：2015-03-16

Applicant: IBM

Inventor： GREINER DAN ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  SCHMIDT DONALD WILLIAM ,  BUSABA FADI YUSUF ,  KUBALA JEFFREY PAUL ,  BRADBURY JONATHAN DAVID ,  HELLER LISA CRANTON ,  SLEGEL TIMOTHY ,  GAINEY CHARLES JR

IPC: G06F9/46

Abstract: A computer system includes a configuration with a core configurable between a single thread (ST) mode and a multithreading (MT) mode. The ST mode addresses a primary thread and the MT mode addresses the primary thread and one or more secondary threads on shared resources of the core. A multithreading facility is configured to control utilization of the configuration to perform a method that includes accessing the primary thread in the ST mode using a core address value and switching from the ST mode to the MT mode. The primary thread or one of the one or more secondary threads is accessed in the MT mode using an expanded address value, where the expanded address value includes the core address value concatenated with a thread address value.

公开(公告)号：IN4837CHN2014A

公开(公告)日：2015-09-18

申请号：IN4837CHN2014

申请日：2014-06-25

Applicant: IBM

Inventor： GAINEY JR CHARLES ,  KUBALA JEFFREY PAUL ,  FARRELL MARK ,  SCHMIDT DONALD WILLIAM ,  PIERCE BERNARD ,  ROGERS ROBERT ,  MULDER JAMES

IPC: G06F9/46

Abstract: A program (e.g. an operating system) is provided a warning that it has a grace period in which to perform a function such as cleanup (e.g. complete stop and/or move a dispatchable unit). The program is being warned in one example that it is losing access to its shared resources. For instance in a virtual environment a guest program is warned that it is about to lose its central processing unit resources and therefore it is to perform a function such as cleanup.

公开(公告)号：SG11201402084VA

公开(公告)日：2014-09-26

申请号：SG11201402084V

申请日：2012-11-13

Applicant: IBM

Inventor： GAINEY JR CHARLES ,  MULDER JAMES ,  FARRELL MARK ,  BERNARD PIERCE ,  SCHMIDT DONALD WILLIAM ,  KUBALA JEFFREY PAUL ,  ROGERS ROBERT

IPC: G06F9/46

Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.

公开(公告)号：MX2014008461A

公开(公告)日：2014-08-27

申请号：MX2014008461

申请日：2012-11-13

Applicant: IBM

Inventor： FARRELL MARK ,  SCHMIDT DONALD WILLIAM ,  GAINEY CHARLES JR ,  KUBALA JEFFREY PAUL ,  PIERCE BERNARD ,  MULDER JAMES ,  ROGERS ROBERT

IPC: G06F9/46

Abstract: Se provee a un programa (por ejemplo, un sistema operativo) una advertencia que tiene un período de gracia en el cual puede efectuar una función, tal como limpieza (por ejemplo, consumar, detener y/o hacer mover una unidad despachable). El programa es advertido, en un ejemplo, que está perdiendo acceso a sus recursos compartidos. Por ejemplo, en un medio ambiente virtual, un programa invitado es advertido que está a punto de perder sus recursos de unidad de procesamiento central y por consiguiente va a efectuar una función, tal como limpieza.

公开(公告)号：AU2012366768A1

公开(公告)日：2014-07-17

申请号：AU2012366768

申请日：2012-11-13

Applicant: IBM

Inventor： GAINEY JR CHARLES ,  KUBALA JEFFREY PAUL ,  FARRELL MARK ,  SCHMIDT DONALD WILLIAM ,  MULDER JAMES ,  PIERCE BERNARD ,  ROGERS ROBERT

IPC: G06F9/46

Abstract: A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, such as cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.

公开(公告)号：AU2010355865B2

公开(公告)日：2014-04-03

申请号：AU2010355865

申请日：2010-11-08

Applicant: IBM

Inventor： SITTMANN III GUSTAV ,  CRADDOCK DAVID ,  GREGG THOMAS ,  SCHMIDT DONALD WILLIAM ,  BELMAR BRENTON FRANCOIS ,  FARRELL MARK ,  OSISEK DAMIAN LEO ,  TARCZA RICHARD ,  EASTON JANET

IPC: G06F9/48

Abstract: The conditions under which adapter interruptions are made pending are controlled. Responsive to an interruption being presented to an operating system, subsequent interruptions are suppressed on all central processing units in the configuration. The operating system processes the interruption, including examining and processing indicators of reported events until the operating system discontinues the suppression. This enables the operating system to control the number of pending interruptions and the number of processors processing those interruptions.