公开(公告)号：FR2326085A1

公开(公告)日：1977-04-22

申请号：FR7623751

申请日：1976-07-28

Applicant: IBM

Inventor： SCHUSTER STANLEY E

IPC: H03K19/096 ,  H03K19/0185 ,  H03K19/173 ,  H03K19/177 ,  H03K19/08 ,  H03K13/00

公开(公告)号：AU2003269997A1

公开(公告)日：2005-04-14

申请号：AU2003269997

申请日：2003-08-26

Applicant: COOK PETER W ,  EMMA PHILIP G ,  JACOBSON HANS M ,  KUDVA PRABHAKAR N ,  SCHUSTER STANLEY E ,  RIVERS JUDE A ,  ZYUBAN VICTOR V ,  IBM ,  BOSE PRADIP ,  CITRON DANIEL M

Inventor： COOK PETER W ,  EMMA PHILIP G ,  JACOBSON HANS M ,  KUDVA PRABHAKAR N ,  SCHUSTER STANLEY E ,  RIVERS JUDE A ,  ZYUBAN VICTOR V ,  BOSE PRADIP ,  CITRON DANIEL M

IPC: G06F1/04 ,  G06F1/32 ,  G06F9/38

Abstract: A synchronous integrated circuit such as a scalar processor or superscalar processor. Circuit components or units are clocked by and synchronized to a common system clock. At least two of the clocked units include multiple register stages, e.g., pipeline stages. A local clock generator in each clocked unit combines the common system clock and stall status from one or more other units to adjust register clock frequency up or down.

公开(公告)号：DE69018053T2

公开(公告)日：1995-09-28

申请号：DE69018053

申请日：1990-12-13

Applicant: IBM

Inventor： CHAPPELL BARBARA A ,  CHAPPELL TERRY I ,  SCHUSTER STANLEY E

IPC: H03K3/011 ,  H03K3/356 ,  H03K17/14 ,  H03K19/0185 ,  H03K3/01

Abstract: CMOS ECL drive circuit for providing regulated ECL logic levels. A CMOS logic circuit (11) is connected by parallel N channel and P channel devices (29, 30) to serially connected N and P channel devices (26, 27). The serially connected N and P channel devices (26, 27) are connected across a CMOS power supply (Vdd, Vss) with gate connections connected to the logic circuit (11). The parallel devices (29, 30) provide a regulating feedback current to one of the serially connected P channel and N channel devices (26, 27) during each of first and second ECL logic states. The feedback current effectively controls the bias on the gate connections of the serially connected P and N channel devices (26, 27). The voltage at the junction of the serially connected P and N channel devices (26, 27) is regulated by each of the parallel connected devices (29, 30).

公开(公告)号：DE69018053D1

公开(公告)日：1995-04-27

申请号：DE69018053

申请日：1990-12-13

Applicant: IBM

Inventor： CHAPPELL BARBARA A ,  CHAPPELL TERRY I ,  SCHUSTER STANLEY E

IPC: H03K3/011 ,  H03K3/356 ,  H03K17/14 ,  H03K19/0185 ,  H03K3/01

Abstract: CMOS ECL drive circuit for providing regulated ECL logic levels. A CMOS logic circuit (11) is connected by parallel N channel and P channel devices (29, 30) to serially connected N and P channel devices (26, 27). The serially connected N and P channel devices (26, 27) are connected across a CMOS power supply (Vdd, Vss) with gate connections connected to the logic circuit (11). The parallel devices (29, 30) provide a regulating feedback current to one of the serially connected P channel and N channel devices (26, 27) during each of first and second ECL logic states. The feedback current effectively controls the bias on the gate connections of the serially connected P and N channel devices (26, 27). The voltage at the junction of the serially connected P and N channel devices (26, 27) is regulated by each of the parallel connected devices (29, 30).

公开(公告)号：CA1009367A

公开(公告)日：1977-04-26

申请号：CA162351

申请日：1973-01-24

Applicant: IBM

Inventor： ALMASI GEORGE S ,  SCHUSTER STANLEY E

IPC: G06F12/16 ,  G06F11/16 ,  G11C11/14 ,  G11C19/08 ,  G11C29/00

公开(公告)号：CA888984A

公开(公告)日：1971-12-21

申请号：CA888984D

Applicant: IBM

Inventor： SCHUSTER STANLEY E ,  CRITCHLOW DALE L