中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

19 records (took 0.018 seconds)

    TWO-DEVICE MEMORY CELL
    12.
    发明专利
    TWO-DEVICE MEMORY CELL 未知

    公开(公告)号：CA1095620A

    公开(公告)日：1981-02-10

    申请号：CA278853

    申请日：1977-05-20

    Applicant: IBM

    Inventor： MIERSCH EKKEHARD F ,  SPAMPINATO DOMINIC P

    IPC: G11C11/405 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/40

    Abstract: TWO-DEVICE MEMORY CELL A two-device memory cell for a memory array comprising a single storage capacitor having its terminals respectively coupled to one end of the respective source-drain paths of a pair of field-effect transistors so as to be in series therewith and float between a pair of bit/sense lines of the memory array respectively coupled to the other end of said paths and thereby provide a differential sense signal. Each of the gate electrodes of said pair of field effect transistors is coupled to the word line of said memory array. The differential sense signal obtained from such an arrangement obviates the need for a dummy cell to provide a reference level for detecting the state of the cell.

    13.
    发明专利
    未知

    公开(公告)号：FR2362493A1

    公开(公告)日：1978-03-17

    申请号：FR7720732

    申请日：1977-06-30

    Applicant: IBM

    Inventor： DENNARD ROBERT H ,  SPAMPINATO DOMINIC P

    IPC: H01L29/78 ,  H01L21/336 ,  H01L21/8234 ,  H01L23/485 ,  H01L23/522 ,  H01L27/06 ,  H01L27/108 ,  H01L29/06 ,  H01L29/423 ,  H01L21/265 ,  H01L27/04

    Abstract: FIELD EFFECT TRANSISTORS AND FABRICATION OF INTEGRATED CIRCUITS CONTAINING THE TRANSISTORS A field effect transistor (FET) wherein the field insulator is nonrecessed with respect to the source and drain regions, wherein the sides of the polysilicon gate electrode are self-aligned with respect to the nonconductive field insulator and neither overlap nor underlap the field insulator. The lateral dimensions and location of the gate correlate directly with the lateral dimensions and location of the channel region of the FET. The gate fabrication technique employed comprises delineating lithographic patterns twice in the same polysilicon layer; whereby the first lithographic pattern delineates regions to be used for sources and drains, and the next lithographic pattern forms the gate regions.

    15.
    发明专利
    未知

    公开(公告)号：FR2280247A1

    公开(公告)日：1976-02-20

    申请号：FR7518149

    申请日：1975-06-03

    Applicant: IBM

    Inventor： DENNARD ROBERT H ,  SPAMPINATO DOMINIC P

    IPC: G11C11/409 ,  G11C7/06 ,  G11C11/24 ,  G11C11/401 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/419 ,  H03F3/70 ,  H03F3/16 ,  G11C29/00

    Abstract: A differential charge transfer amplifier which functions as a sensing and regenerating circuit responsive to binary information represented by the level of charge in a stored charge memory cell is disclosed. The sense amplifier includes a pair of dummy cells and bucket brigade amplifiers which are connected on either side of a dynamic latching circuit which includes a plurality of actuable gate devices, which may be field effect transistors. A bit/sense line of the array is divided into two equal sections which are respectively connected to either side of the sense amplifier. The operation of the amplifier is cyclic, including a precharge period, a sensing period, a rewrite period and a restore period, after which the amplifier is in its original state. A feature of the amplifier is that it consumes no d.c. power other than leakage and has high sensitivity due to a charge transfer feature. Also, during the operation of the circuit, energy remaining in one of the bit line sections after rewriting is utilized to pre-bias both bit line sections to an initial level. As a result, this allows better control of the precharge level on the bit/sense line and in so doing, the power requirements are substantially reduced. At the same time, a dummy cell is charged to the potential of the now balanced bit lines.

    16.
    发明专利
    未知

    公开(公告)号：FR2355358A1

    公开(公告)日：1978-01-13

    申请号：FR7714010

    申请日：1977-05-03

    Applicant: IBM

    Inventor： MIERSCH EKKEHARD F ,  SPAMPINATO DOMINIC P

    IPC: G11C11/405 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/40 ,  G11C7/00

    Abstract: 1523094 Transistor memory cells INTERNATIONAL BUSINESS MACHINES CORP 25 April 1977 [17 June 1976] 17190/77 Heading H3T A memory cell comprises a single storage capacitor C, coupled in a series circuit including the source-drain paths of two FET's 1, 3 between two bit/sense lines B/S0, B/S1, the gate electrodes of the two transistors being coupled to the word line. The cell provides a differential signal and obviates the need for a dummy cell to provide a reference signal for detecting the cell state. To write data into the cell, the transistors 1,3 are turned on to allow capacitor C s to charge in one sense or the other, depending on whether a "0" or a " 1" is being written in. The transistors are then turned off to leave the capacitor floating. To read, the transistors are again turned on, and the differential voltage across the capacitor is sensed between the bit/sense lines.

Patent Agency Ranking