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公开(公告)号：ES2160770T3
公开(公告)日：2001-11-16
申请号：ES96304352
申请日：1996-06-10
Applicant: IBM
Inventor： HASSNER MARTIN AURELIANO , TAMURA TETSUYA , WINOGRAD SHMUEL
Abstract: Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.
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公开(公告)号：DE69424229D1
公开(公告)日：2000-06-08
申请号：DE69424229
申请日：1994-06-27
Applicant: IBM
Inventor： HASSNER MARTIN AURELIANO , KARNIN EHUD DOV , SCHWIEGELSHOHN UWE , TAMURA TETSUYA
Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer 22 comprises an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.
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公开(公告)号：SG42404A1
公开(公告)日：1997-08-15
申请号：SG1996009788
申请日：1996-05-13
Applicant: IBM
Inventor： HASSNER MARTIN AURELIANO , TAMURA TETSUYA , WINOGRADE SHMUEL
Abstract: Parallel ML processing of an analog signal in a RLL-coded channel in which (1) vectors for a current state of the channel and the next state of the channel are computed using Walsh transform vector coefficients of the analog signal; (2) current state vectors and next state vectors and values of vectors precomputed in analog matched filters are used to generate vector scalar products which are compared against preselected threshold values for generating binary decision outputs that are used in digital sequential finite state machines to generate ML symbol decisions; and (3) ML symbol decisions are fed back and used to subtract the intersymbol interference value of the current state vector from the vector of the next state to transform the next state vector into an updated current state vector.
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公开(公告)号：BR9402666A
公开(公告)日：1995-05-02
申请号：BR9402666
申请日：1994-07-08
Applicant: IBM
Inventor： HASSNER MARTIN AURELIANO , KARNIN EHUD DOV , SCHWIEGELSHOHN UWE , TAMURA TETSUYA
Abstract: An apparatus and method for executing a sequential data compression algorithm that is especially suitable for use where data compression is required in a device (as distinguished from host) controller. A history buffer 22 comprises an array of i identical horizontal slice units. Each slice unit stores j symbols to define j separate blocks in which the symbols in each slice unit are separated by exactly i symbols. Symbols in a string of i incoming symbols are compared by i comparators in parallel with symbols previously stored in the slice units to identify matching sequences of symbols. A control unit controls execution of the sequential algorithm to condition the comparators to scan symbols in parallel but in each of the blocks sequentially and cause matching sequences and nonmatching sequences of symbols to be stored in the array. The parameters i and j are selected to limit the number of comparators required to achieve a desired degree of efficiency in executing the algorithm based upon a trade-off of algorithm execution speed versus hardware cost. A priority encoder calculates from signals output by the slice units each j,i address in which a matching sequence is identified, but it outputs the address of only one (such as the smallest) of these addresses.
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公开(公告)号：JP2000224049A
公开(公告)日：2000-08-11
申请号：JP1346899
申请日：1999-01-21
Applicant: IBM
Inventor： NAKAMURA AKIO , TAMURA TETSUYA , DEMURA MASAYUKI
Abstract: PROBLEM TO BE SOLVED: To detect error correction in a short time and to execute error correction by adding an error correction code to one or more error detection code blocks to which the error detection code is attached, calculating an error value by using the error correction code respectively included in data series, correcting the syndrome value of the error detection code according to the value and detecting error occurrence. SOLUTION: A selector 126 operates in accordance with the control of a chain searching part 112 of an error correction block 10 and selects a root inputted from a position counter 110, when it is shown that there is no error in detected data. Then, it outputs it to error detection code EDC correction difference calculating parts 14a and 14b and a syndrome correction difference calculating part 18. A selector 128 operates in accordance with the control of the part 112 of the block 10, selects a numerical value 0 when it is shown that an error does not exist in detected data, selects size data when an error exists in the detected data and outputs to the parts 14a and 14b.
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Patent Agency Ranking
公开(公告)号：JPH11274941A
公开(公告)日：1999-10-08
申请号：JP2487598
申请日：1998-02-05
Inventor： NAGURA HIROHISA , DEMURA MASAYUKI , TANAKA KEISUKE , TAMURA TETSUYA
CPC classification number: G06F11/1008 , G11B20/10 , G11B20/18 , H03M13/1515 , H03M13/29 , H03M13/2909 , H03M13/293
Abstract: PROBLEM TO BE SOLVED: To shorten the total processing time needed for correction of errors by taking out two position data adjacent to each other in a single line that is sorted as an erased line and also two information data related to the position data and then repetitively correcting two position data based on the patterns included in those position and information data until all lines are corrected. SOLUTION: The coding data on a row 1 included in every group which are stored in the memory sections 14 and 15 and taken out of a main memory 12 are sent to a wrong data position/pattern generator 16 via a line 24. Thus, the information blocks are generated. The generator 16 detects via an erased line pointer of a register 32 whether the wrong data under processing belong to an erased line or non-erased line. Then generator 16 calculates the wrong data position of the erased line to generate an information block, including a bit pattern that corrects the wrong data position and sends the information block to a memory section 14A of a buffer memory 13 to assemble the rows. It is checked whether all rows have been processed, and these operations are repeated until all the rows are have been corrected.
Abstract translation: 要解决的问题：通过在排列为擦除行的单行中取出彼此相邻的两个位置数据以及与位置数据相关的两个信息数据，然后重复地缩短校正错误所需的总处理时间 基于包括在那些位置和信息数据中的模式来校正两个位置数据，直到所有行被校正。 解决方案：存储在存储器部分14和15中并从主存储器12中取出的每个组中包括的行1上的编码数据经由线路24被发送到错误的数据位置/模式发生器16.因此， 生成信息块。 发生器16经由寄存器32的擦除行指针检测处理中的错误数据是否属于擦除行或未擦除行。 然后，发生器16计算擦除行的错误数据位置，以产生信息块，包括校正错误数据位置的位模式，并将信息块发送到缓冲存储器13的存储器部分14A以组合行。 检查是否已经处理了所有行，并重复这些操作，直到所有行已被更正。
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公开(公告)号：JP2004171751A
公开(公告)日：2004-06-17
申请号：JP2003384262
申请日：2003-11-13
Applicant: Internatl Business Mach Corp
, インターナショナル・ビジネス・マシーンズ・コーポレーションInternational Business Maschines Corporation Inventor： ASANO HIDEO , HASSNER MARTIN AURELIANO , HEISE NYLES NORBERT , HETZLER STEVEN R , TAMURA TETSUYA
IPC: G06F11/10 , G06F11/00 , G11B5/09 , G11B20/18 , H03M13/00 , H03M13/03 , H03M13/11 , H03M13/15 , H03M13/29 , H03M13/47
CPC classification number: H03M13/25 , G06F11/1076 , G06F2211/104 , H03M13/1515 , H03M13/29 , H03M13/47
Abstract: PROBLEM TO BE SOLVED: To provide an encoding system and related method which prevent erroneous correction by parity sector correction in on-drive RAID system or the like.
SOLUTION: In this system, A parity cluster block being a perfect cluster itself receiving C3 protection is added. There is seldom possibility of providing defective data even if "jami" error is caused by providing such functions as C4 level correction of a cluster level by a parity sector checked and verified by C3 check having a high reliability level and checking compatibility of the cluster block. Scrub algorithm avoids read-out - change - write-in operation by delaying finish of C2 and C3 check until a storage device becomes an idle state.
COPYRIGHT: (C)2004,JPO-
公开(公告)号：JP2003141822A
公开(公告)日：2003-05-16
申请号：JP2001325696
申请日：2001-10-23
Applicant: IBM
Inventor： KATO KATSUHIKO , FUKUSHIMA YUKIO , UEDA TETSUO , NAKAGAWA YUZO , SHIMONO EMI , KURODA TAKASHI , KOBAYASHI SHUNSUKE , TAMURA TETSUYA , SAI FUMINORI
Abstract: PROBLEM TO BE SOLVED: To contribute to the generation of correct read data by increasing the probability of error corrections. SOLUTION: Reading about the same sector is performed multiple times, the majority is taken in the same address (Address), and the most frequent value is considered to be a genuine data value. For example, in an address 00, '00' is treated as a genuine data value.
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公开(公告)号：JP2001044853A
公开(公告)日：2001-02-16
申请号：JP18156299
申请日：1999-06-28
Applicant: IBM
Inventor： KATO KATSUHIKO , NAKAMURA AKIO , TAMURA TETSUYA
Abstract: PROBLEM TO BE SOLVED: To provide a chain search circuit that shourtens the time required for chain search without having to increase the number of gates of a multiplication result storage circuit, when conducting pipeline processing for quickening chain search. SOLUTION: A chain search circuit 55 is provided with flip-flop circuits(FF) 101a to 101c, that are provided corresponding to each term of an error location polynomial, store each coefficient of the error location polynomial for an initial value and store a multiplication result of multiplying an element of a Galois field with each coefficient, high-order fixed multipliers 103a to 103c that multiply the powers (αn) of the highest order αrespectively in parallel corresponding to the flip-flop circuits(FF) 101a to 101c, and low order fixed multipliers 104a to 104c that respectively multiply the powers (αn-1) of the lower order α, and the flip-flop circuits (FF) 101a to 101c latch only the result of products of the high-order fixed multipliers 103a to 103c that multiply the powers (αn) of the highest order α.
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公开(公告)号：JPH09198809A
公开(公告)日：1997-07-31
申请号：JP795196
申请日：1996-01-22
Applicant: IBM
Inventor： TAMURA TETSUYA
Abstract: PROBLEM TO BE SOLVED: To obtain a method for effectively preventing error propagation in the case of using a PRML (maximum liklihood decoding method) in a decoder having error discriminating means to prevent the error propagation of the signal read from a recording medium. SOLUTION: The value of the signal read from a recording medium is multiplied and added as prescribed, and whether the calculated result falls within a predetermined range or not is discriminated. Boundary detectors 1 to 4 judge whether the outputs from selection signal generators 1 to 4, decoded result, output of a new product-sum arithmetic unit F and outputs of F1, F2, F3 coincide with error conditions or not. That is, it judges whether the decision boundary used to decide the decoded results of respective its is erroneous or not. If it is erroneous, an error signal is generated to prevent the error propagation, and a signal is sent to next bit selection signal generator.
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