公开(公告)号：GB2525430B

公开(公告)日：2016-07-13

申请号：GB201407279

申请日：2014-04-25

Applicant: IBM

Inventor： THOMAS MITTELHOLZER ,  NIKOLAOS PAPANDREOU ,  THOMAS PARNELL ,  CHARALAMPOS POZIDIS

IPC: H04L1/00 ,  G06F11/10 ,  H03M13/03

公开(公告)号：GB2533501A

公开(公告)日：2016-06-22

申请号：GB201603366

申请日：2014-07-28

Applicant: IBM

Inventor： ROY D CIDECIYAN ,  ROBERT A HUTCHINS ,  THOMAS MITTELHOLZER ,  KEISUKE TANAKA

IPC: H03M13/29 ,  H03M13/15 ,  H03M13/37

Abstract: In one embodiment, a system for combination error and erasure decoding for product codes includes a processor and logic integrated with and/or executable by the processor, the logic being configured to receive captured data, generate erasure flags for the captured data and provide the erasure flags to a C2 decoder, set a stop parameter to be equal to a length of C1 codewords in a codeword interleave used to encode the captured data, and selectively perform, in an iterative process, error or erasure C1 decoding followed by error or erasure C2 decoding until decoding is successful or unsuccessful. In more embodiments, a method and/or a computer program product may be used for combination error and erasure decoding for product codes.