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    salvar/ restaurar registradores selecionados em processamento transacional
    11.
    发明专利
    salvar/ restaurar registradores selecionados em processamento transacional 未知

    公开(公告)号：BR112014031415B1

    公开(公告)日：2021-08-10

    申请号：BR112014031415

    申请日：2012-11-26

    Applicant: IBM

    Inventor： CHRISTIAN JACOBI ,  DAN GREINER ,  TIMOTHY SLEGEL

    IPC: G06F9/308 ,  G06F9/312 ,  G06F13/40

    Abstract: salvar/ restaurar registradores selecionados em processamento transacional. uma instrução de iniciar transação inicia a execução de uma transação e inclui uma máscara de salvar registrador geral que tem bits os quais, quando definidos, indicam registradores a serem salvos no caso em que a transação é abortada. no início da transação, os conteúdos dos registradores são salvos na memória não acessível para o programa e, se a transação é abortada, os conteúdos salvos são copiados para os registradores.

    Conditional Instruction End Operation
    13.
    发明专利
    Conditional Instruction End Operation 未知

    公开(公告)号：GB2542278B

    公开(公告)日：2020-08-05

    申请号：GB201616977

    申请日：2015-03-11

    Applicant: IBM

    Inventor： DAN GREINER ,  TIMOTHY SLEGEL ,  CHRISTIAN JACOBI ,  DONALD WILLIAM SCHMIDT ,  MARCEL MITRAN

    IPC: G06F9/30 ,  G06F9/38

    Abstract: A conditional instruction end facility is provided that allows completion of an instruction to be delayed. In executing the machine instruction, an operand is obtained, and a determination is made as to whether the operand has a predetermined relationship with respect to a value. Based on determining that the operand does not have the predetermined relationship with respect to the value, the obtaining and the determining are repeated. Based on determining that the operand has the predetermined relationship with respect to the value, execution of the instruction is completed. The obtaining the operand, the determining whether the operand has the predetermined relationship, the based on determining that the operand does not have the predetermined relationship with respect to the value, repeating the obtaining and the determining, and the based on determining that the operand has the predetermined relationship with respect to the value, completing execution of the instruction are performed as part of a single instruction having one operation code.

    Non-quiescing key setting facility
    15.
    发明专利
    Non-quiescing key setting facility 未知

    公开(公告)号：GB2488458B

    公开(公告)日：2017-08-23

    申请号：GB201207328

    申请日：2010-12-14

    Applicant: IBM

    Inventor： TIMOTHY SLEGEL ,  DAN GREINER ,  CHUNG-LUNG KEVIN SHUM ,  CHRISTIAN JACOBI

    IPC: G06F9/30 ,  G06F9/38 ,  G06F12/14

    Abstract: A non-quiescing key setting facility is provided that enables manipulation of storage keys to be performed without quiescing operations of other processors of a multiprocessor system. With this facility, a storage key, which is accessible by a plurality of processors of the multiprocessor system, is updated absent a quiesce of operations of the plurality of processors. Since the storage key is updated absent quiescing of other operations, the storage key may be observed by a processor as having one value at the start of an operation performed by the processor and a second value at the end of the operation. A mechanism is provided to enable the operation to continue, avoiding a fatal exception.

    AREA DE CONTROL PARA GESTIONAR MULTIPLES SUBPROCESOS EN UNA COMPUTADORA.
    19.
    发明专利
    AREA DE CONTROL PARA GESTIONAR MULTIPLES SUBPROCESOS EN UNA COMPUTADORA. 未知

    公开(公告)号：MX2016012531A

    公开(公告)日：2016-12-20

    申请号：MX2016012531

    申请日：2015-03-16

    Applicant: IBM

    Inventor： GREINER DAN ,  SCHMIDT DONALD WILLIAM ,  OSISEK DAMIAN LEO ,  GAINEY JR CHARLES ,  FADI YUSUF BUSABA ,  MARK FARRELL ,  JEFFREY PAUL KUBALA ,  JONATHAN DAVID BRADBURY ,  LISA CRANTON HELLER ,  TIMOTHY SLEGEL

    IPC: G06F9/455 ,  G06F9/50

    Abstract: Un sistema de computadora incluye una configuración de máquina virtual (VM) con uno o más núcleos. Cada núcleo se hablita para operar en un modo de subprocesamiento individual (ST) o un modo de subprocesamiento múltiple (MT). El modo ST consiste de un subproceso individual y el modo MT consiste de una pluralidad de subprocesos en recursos compartidos de un núcleo respectivo. El sistema de computadora incluye un área de control de sistema orientada al núcleo (COSCA) que tiene un área común que representa todos los núcleos de la configuración de VM y áreas de descripción de núcleo separadas para cada uno de los núcleos en la configuración de VM. Cada área de descripción de núcleo indica una ubicación de una o más áreas de descripción de subproceso cada una que representa un subproceso dentro del núcleo respectivo, y cada área de descripción de subproceso indica una ubicación de una descripción de estado del subproceso respectivo.

    Detection of alteration of storage keys used to protect memory
    20.
    发明专利
    Detection of alteration of storage keys used to protect memory 未知

    公开(公告)号：GB2596007A

    公开(公告)日：2021-12-15

    申请号：GB202113006

    申请日：2020-02-14

    Applicant: IBM

    Inventor： TIMOTHY SLEGEL ,  JONATHAN DAVID BRADBURY ,  BRUCE CONRAD GIAMEI ,  JAMES MULDER ,  PETER JEREMY RELSON

    IPC: G06F12/1027

    Abstract: Detection of alteration of storage keys used to protect memory includes determining whether a storage key alteration event has occurred within a processor of a computing environment. The determining includes checking whether one or more selected fields of a storage key have been updated. The storage key is associated with a block of memory and controls access to the block of memory. Based on the checking indicating that the one or more selected fields of the storage key have been updated, a storage key alteration event has been detected. Based on determining the storage key alteration event has occurred, a notification is provided.

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