公开(公告)号：AT490555T

公开(公告)日：2010-12-15

申请号：AT06819175

申请日：2006-10-27

Applicant: IBM

Inventor： HSU LOUIS ,  MANDELMAN JACK ,  TONTI WILLIAM

IPC: H01L23/525

Abstract: In a first aspect, a first apparatus is provided. The first apparatus is an eFuse including (1) a semiconducting layer above an insulating oxide layer of a substrate; (2) a diode formed in the semiconducting layer; and (3) a silicide layer formed on the diode. Numerous other aspects are provided.

公开(公告)号：DE10358356A1

公开(公告)日：2004-07-15

申请号：DE10358356

申请日：2003-12-12

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： JACUNSKI MARK D ,  TONTI WILLIAM ,  MCSTAY KEVIN ,  MAFFITT THOMAS M ,  HOUGHTON RUSSEL

IPC: G11C8/08

Abstract: An apparatus and method for wordline voltage compensation in integrated memories is provided, where the apparatus includes an array threshold voltage ("VT") monitor, a wordline on voltage ("Vpp") generator in signal communication with the threshold voltage monitor for providing a wordline on voltage responsive to a change in the monitored array threshold voltage, and a wordline off voltage ("VWLL") generator in signal communication with the threshold voltage monitor for providing a wordline off voltage responsive to a change in the monitored array threshold voltage; and where the corresponding method for compensating each of a wordline on signal and a wordline off signal in correspondence with an array threshold signal includes monitoring an array threshold signal, generating a wordline on signal responsive to the monitored array threshold signal, and generating a wordline off signal responsive to the monitored array threshold signal.

公开(公告)号：DE10342028A1

公开(公告)日：2004-03-25

申请号：DE10342028

申请日：2003-09-11

Applicant: INFINEON TECHNOLOGIES AG ,  IBM

Inventor： CHIDAMBARRAO DURESETI ,  FREY ULRICH ,  HEDGE SURYANARAYAN ,  TONTI WILLIAM

IPC: H01L21/82 ,  H01L23/525 ,  H01L27/10 ,  H01L21/768

Abstract: An integrated circuit is manufactured by doping portion of semiconductor substrate with nitrogen and a charge carrier dopant source, forming a thin dielectric on the doped portion of the substrate, forming a first separated from the substrate by the thin dielectric, and forming a second conductor coupled to the doped portion of the substrate. The thin dielectric is subjected to breakdown upon application of a breakdown voltage. An Independent claim is also included for an integrated circuit including an anti-fuse.