公开(公告)号：DE3784120T2

公开(公告)日：1993-08-12

申请号：DE3784120

申请日：1987-06-30

Applicant: IBM

Inventor： CROUSE WILLIAM GEORGE ,  WARE MALCOLM SCOTT

IPC: G10L19/02 ,  H04B1/66

Abstract: Sub-band speech coders that depend on allocation of available bit capacity of a transmission medium to provide high quality speech coding for digital transmission are well known. The present invention utilizes one or more bit allocation tables to dynamically distribute the channel bit capacity bandwidth among the frequency bands according to the desired output quality of speech rather than by means of complex algorithms or simulation techniques. Multiple bit assignment tables are provided to allow various quality levels to be traded off as increasing bit rate demands are placed upon the transmission system. The technique is used for a single coder to achieve a minimum bit rate for a desired given level of subjective quality in speech output or may be used in a shared bit resource to maintain equal and minimum quality degradation for all users. The quality tables determine the number of bits to be dropped from the encoded representation of each signal sample to minimize the transmission load for a given coder without sacrificing speech quality to an unacceptable degree. Table entries are arranged based on the overall band peak energy level and on the sub-band peak energy distribution or spectrum as it is known in the field.

公开(公告)号：GB2365666A

公开(公告)日：2002-02-20

申请号：GB0107870

申请日：2001-03-28

Applicant: IBM

Inventor： CORL JR EVERETT ARTHUR ,  DAVIS GORDON TAYLOR ,  JEFFRIES CLARK DEBS ,  WARE MALCOLM SCOTT

IPC: H04L12/56 ,  H04L29/06 ,  H04Q11/04

Abstract: A method and system for testing a plurality of filter rules in a computer system is disclosed. The plurality of filter rules are used with a key that is capable of matching at least one of the plurality of filter rules. The at least one filter rule corresponds to at least one action. The computer system has a cache including a plurality of bins and a decision tree. The method and system include searching a plurality of stored keys in the cache for the key. Preferably, this search of the cache for the key includes determining whether a stored key exactly matches the key. A plurality of stored filter rules corresponds to the plurality of stored keys. A plurality of stored actions corresponds to the plurality of stored filter rules. The cache stores each of the plurality of stored keys and at least one stored action in each bin of a portion of the bins. The method and system also include obtaining the at least one action from the cache if the key is found in plurality of stored keys and otherwise obtaining the at least one action using the decision tree. Preferably, searches of the decision tree and cache start simultaneously. The decision tree search is terminated if the key is found in the cache. The cache is written to if the at least one action is obtained using the decision tree, but preferably only if the at least one filter rule has a priority of one.

公开(公告)号：HU219533B

公开(公告)日：2001-05-28

申请号：HU9400792

申请日：1992-08-26

Applicant: IBM

Inventor： CARMON DONALD EDWARD ,  CROUSE WILLIAM GEORGE ,  WARE MALCOLM SCOTT

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

公开(公告)号：DE69220169D1

公开(公告)日：1997-07-10

申请号：DE69220169

申请日：1992-08-28

Applicant: IBM

Inventor： MURRAY JACK THOMAS ,  UNGERBOECK GOTTFRIED ,  WARE MALCOLM SCOTT

IPC: H04L27/00 ,  H04L27/22 ,  H04L25/38

公开(公告)号：AT149259T

公开(公告)日：1997-03-15

申请号：AT92918307

申请日：1992-08-26

Applicant: IBM

Inventor： CARMON DONALD EDWARD ,  CROUSE WILLIAM GEORGE ,  WARE MALCOLM SCOTT

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10 ,  G06F9/46

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.

公开(公告)号：HUT68084A

公开(公告)日：1995-05-29

申请号：HU9400792

申请日：1992-08-26

Applicant: IBM

Inventor： CROUSE WILLIAM GEORGE ,  CARMON DONALD EDWARD ,  WARE MALCOLM SCOTT

IPC: G06F9/50 ,  G06F13/28 ,  G06F17/10

Abstract: A multi-media user task (host) computer is interfaced to a high speed DSP which provides support functions to the host computer via an interprocessor DMA bus master and controller. Support of multiple dynamic hard real-time signal processing task requirements are met by posting signal processor support task requests from the host processor through the interprocessor DMA controller to the signal processor and its operating system. The signal processor builds data transfer packet request execution lists in a partitioned queue in its own memory and executes internal signal processor tasks invoked by users at the host system by extracting signal sample data from incoming data packets presented by the interprocessor DMA controller in response to its execution of the DMA packet transfer request queues built by the signal processor in the partitioned queue. Processed signal values etc. are extracted from signal processor memory by the DMA interprocessor controller executing the partitioned packet request lists and delivered to the host processor. A very large number of packet transfers in support of numerous user tasks and implementing a very large number of DMA channels is thus made possible while avoiding the need for arbitration between the channels on the part of the signal processor or the host processor.