公开(公告)号：HU0100013A2

公开(公告)日：2001-05-28

申请号：HU0100013

申请日：1998-10-14

Applicant: IBM

Inventor： BORKENHAGEN JOHN MICHAEL ,  EICKEMEYER RICHARD JAMES ,  FLYNN WILLIAM THOMAS ,  LEVENSTEIN SHELDON BERNARD ,  WOTTRENG ANDREW HENRY

IPC: G06F12/08 ,  G06F9/38 ,  G06F9/46 ,  G06F9/48

Abstract: A system and method for performing computer processing operations in a data processing system includes a multithreaded processor and thread switch logic. The multithreaded processor is capable of switching between two or more threads of instructions which can be independently executed. Each thread has a corresponding state in a thread state register depending on its execution status. The thread switch logic contains a thread switch control register to store the conditions upon which a thread switch will occur. The thread switch logic has a time-out register which forces a thread switch when execution of the active thread in the multithreaded processor exceeds a programmable period of time. Thread switch logic also has a forward progress count register to prevent repetitive thread switching between threads in the multithreaded processor. Thread switch logic also is responsive to a software manager capable of changing the priority of the different threads and thus superseding thread switch events.

公开(公告)号：GB2324393A

公开(公告)日：1998-10-21

申请号：GB9803673

申请日：1998-02-24

Applicant: IBM

Inventor： LARSEN TROY DALE ,  RANDOLPH JACK CHRIS ,  WOTTRENG ANDREW HENRY

IPC: G06F11/34

Abstract: A method and system for performance monitoring within a multithreaded processor are provided. The system includes a processor responsive to instructions within first and second threads and a performance monitor that separately records a first event generated by the processor in response to the first thread and a second event generated by the processor in response to the second thread. In one embodiment, the processor has first and second modes of operation. In this embodiment, when the performance monitor is operating in the first mode, a first counter within the performance monitor increments in response to each occurrence of the first event and a second counter within the performance monitor increments in response to each occurrence of the second event. Alternatively, when the performance monitor is operating in the second mode, the first counter increments in response to each occurrence of the first event and in response to each occurrence of the second event.

公开(公告)号：DE69029995T2

公开(公告)日：1997-08-21

申请号：DE69029995

申请日：1990-10-09

Applicant: IBM

Inventor： LEMAIRE CHARLES ARTHUR ,  WOTTRENG ANDREW HENRY

IPC: G06F9/30 ,  G06F9/46 ,  G06F15/16 ,  G06F15/177

Abstract: A computer system in which each of certain critical instructions, all performing multiple main storage accesses to shared data, have the appearance of executing required main storage accesses atomically with respect to a predefined set or class of instructions. The instructions in each set, referred to as relatively atomic instructions, are grouped together based on the data structure or object class they affect. The computer system comprises (a) shared memory means (203); (b) a plurality of processors (201, 202,..., n) coupled to said shared memory means, wherein each processor has an instruction set divided into a plurality of instruction classes; (c) means for constraining an instruction in one of said classes running on one of said plurality of processors, to run atomically relative to any instruction in said class running on any other of said plurality of processors in said system; (d) means for signalling (280, 281, 282) between said processors to indicate when an instruction in one of said classes is running and for providing an indication of which particular class the instruction is a member of; and (e) means for selectively delaying the operation of all other instructions in said particular class on every other processor in said system.

公开(公告)号：PL193285B1

公开(公告)日：2007-01-31

申请号：PL34009598

申请日：1998-10-14

Applicant: IBM

Inventor： BORKENHAGEN JOHN MICHAEL ,  EICKEMEYER RICHARD JAMES ,  FLYNN WILLIAM THOMAS ,  WOTTRENG ANDREW HENRY

IPC: G06F9/38 ,  G06F12/08 ,  G06F9/46 ,  G06F9/48

公开(公告)号：MX151497A

公开(公告)日：1984-12-04

申请号：MX18804981

申请日：1981-06-29

Applicant: IBM

Inventor： BODNER RONALD EUGENE ,  CROOKS THOMAS LEE ,  WOTTRENG ANDREW HENRY

IPC: G06F9/34 ,  G06F12/04 ,  G11C11/065

Abstract: Storage addressing control apparatus is structured to provide either byte or word addressing of storage organized on a two byte word basis. The storage address register (6) is made shiftable whereby for byte operations it is shifted, and the bit (SAR BIT 16) shifted out of the register is used for byte selection. The contents of the storage address register are used to address storage (10) for both word and byte addressing, and no change is required. The storage access, however, for byte addressing takes place after the shift is completed and the timing is adjusted to account for the shift operation. Gate control logic is modified to facilitate the byte selection.