公开(公告)号：DE102004037164A1

公开(公告)日：2006-03-23

申请号：DE102004037164

申请日：2004-07-30

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER ,  JAKOBS ANDREAS

IPC: H03L7/081 ,  G11C11/4063

Abstract: A device for the regulated delay of a clock signal is proposed, which comprises a delay means in order to generate a delayed clock signal, and comparison means for the phase comparison of the delayed clock signal with a reference clock signal. The reference clock signal is in this connection preferably formed by the clock signal or is derived therefrom. On the basis of a comparison signal generated by the comparison means, a digital control signal is generated for controlling the delay means. The comparison means are configured so as to generate the comparison signal as a digitally coded signal that has a pulse duty ratio and a frequency that are determined by a further clock signal that is generated independently of the first clock signal, and that preferably has twice the frequency of the first clock signal.

公开(公告)号：DE10337084B4

公开(公告)日：2006-01-12

申请号：DE10337084

申请日：2003-08-12

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BONHAUS JOERG ,  DUDA THOMAS ,  GREGORIUS PETER ,  GAZSI LAJOS

IPC: H03C1/62 ,  H04B1/10 ,  H04B17/00 ,  H04L25/08 ,  H04L27/36 ,  H04L29/08

Abstract: Generator signals are generated by unit (10), providing signals with certain signal form determined in dependence on preset signal norm form. Matching unit (20) adapts generated signal form to properties of signal transmission channel. Signal generating and matching units are so fitted that signals transmitted, via transmission channel, from matching unit are in signal form corresponding to preset signal norm form. Signal matching and generating units are of digital type.

公开(公告)号：DE102004058915A1

公开(公告)日：2005-07-14

申请号：DE102004058915

申请日：2004-12-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： DALT NICOLA DA ,  GREGORIUS PETER

IPC: H03M1/06 ,  H03M1/76 ,  H01L27/10 ,  H01L23/528 ,  H03M1/74

公开(公告)号：SE0402045D0

公开(公告)日：2004-08-18

申请号：SE0402045

申请日：2004-08-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENGEL BERNHARD ,  GREGORIUS PETER

IPC: H03L7/089 ,  H03L7/091 ,  H04L7/033 ,  H04L25/04 ,  H04L

Abstract: A CDR circuit arrangement, for example for a transceiver module, features a data recovery unit ( 4 ) for the recovery of the data contained in a received signal (DATA) by scanning this received data signal, and a phase evaluation unit for the determination of a suitable phase position for the scanning carried out by the data recovery unit ( 4 ). The phase evaluation unit comprises a scanning device ( 1 ) for the oversampling of a the received data signal (DATA) in accordance with several different scanning phases (P 0 -P 6 ), a phase detector device ( 2 ) for the evaluation of the scanning values (A 0 -A 6 ) accordingly prepared by the scanning device ( 1 ), in order thereby to derive intermediate signals (UP 1 -UP 3, DN 1 -DN 3 ), which classify the phase error during the scanning of the data signal by the scanning device ( 1 ) in respect of its size and direction of deviation, as well as a filter device ( 3 ), in order to subject the intermediate signals (UP 1 -UP 3, DN 1 -DN 3 ) generated by the phase detector device ( 2 ) to a weighted filtering process. In this situation, a setting signal (DeltaP) is generated by the filter device ( 3 ) for the subsequent regulation and control of the scanning phases (P 0 -P 6 ) of the scanning device ( 1 ).

公开(公告)号：AU2002325915A1

公开(公告)日：2003-09-22

申请号：AU2002325915

申请日：2002-07-26

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENGL BERNHARD ,  GREGORIUS PETER

IPC: H03L7/089 ,  H03L7/091 ,  H04L7/033 ,  H04L25/04

Abstract: A CDR circuit arrangement, for example for a transceiver module, features a data recovery unit ( 4 ) for the recovery of the data contained in a received signal (DATA) by scanning this received data signal, and a phase evaluation unit for the determination of a suitable phase position for the scanning carried out by the data recovery unit ( 4 ). The phase evaluation unit comprises a scanning device ( 1 ) for the oversampling of a the received data signal (DATA) in accordance with several different scanning phases (P 0 -P 6 ), a phase detector device ( 2 ) for the evaluation of the scanning values (A 0 -A 6 ) accordingly prepared by the scanning device ( 1 ), in order thereby to derive intermediate signals (UP 1 -UP 3, DN 1 -DN 3 ), which classify the phase error during the scanning of the data signal by the scanning device ( 1 ) in respect of its size and direction of deviation, as well as a filter device ( 3 ), in order to subject the intermediate signals (UP 1 -UP 3, DN 1 -DN 3 ) generated by the phase detector device ( 2 ) to a weighted filtering process. In this situation, a setting signal (DeltaP) is generated by the filter device ( 3 ) for the subsequent regulation and control of the scanning phases (P 0 -P 6 ) of the scanning device ( 1 ).

公开(公告)号：DE10207315A1

公开(公告)日：2003-09-18

申请号：DE10207315

申请日：2002-02-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： ENGL BERNHARD ,  GREGORIUS PETER

IPC: H03L7/089 ,  H03L7/091 ,  H04L7/033 ,  H04L25/04

Abstract: A CDR circuit arrangement, for example for a transceiver module, features a data recovery unit ( 4 ) for the recovery of the data contained in a received signal (DATA) by scanning this received data signal, and a phase evaluation unit for the determination of a suitable phase position for the scanning carried out by the data recovery unit ( 4 ). The phase evaluation unit comprises a scanning device ( 1 ) for the oversampling of a the received data signal (DATA) in accordance with several different scanning phases (P 0 -P 6 ), a phase detector device ( 2 ) for the evaluation of the scanning values (A 0 -A 6 ) accordingly prepared by the scanning device ( 1 ), in order thereby to derive intermediate signals (UP 1 -UP 3, DN 1 -DN 3 ), which classify the phase error during the scanning of the data signal by the scanning device ( 1 ) in respect of its size and direction of deviation, as well as a filter device ( 3 ), in order to subject the intermediate signals (UP 1 -UP 3, DN 1 -DN 3 ) generated by the phase detector device ( 2 ) to a weighted filtering process. In this situation, a setting signal (DeltaP) is generated by the filter device ( 3 ) for the subsequent regulation and control of the scanning phases (P 0 -P 6 ) of the scanning device ( 1 ).

公开(公告)号：DE10141597A1

公开(公告)日：2003-03-20

申请号：DE10141597

申请日：2001-08-24

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER ,  GAZSI LAJOS

IPC: H03M1/18 ,  H04B3/14 ,  H04L25/08 ,  H04L25/20 ,  H04B3/04

公开(公告)号：CA2453146A1

公开(公告)日：2003-01-30

申请号：CA2453146

申请日：2002-06-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER

IPC: H03F3/45 ,  H04L25/02 ,  H04L25/20 ,  H04M1/00 ,  H04M3/00

Abstract: The invention relates to a line driver, wherein an input current (IINN) feed s a node (K1) which is connected to an input of an amplifier (OTA1). A second input of the amplifier (OTA1) is supplied with a reference voltage (VSGND). The amplifier (OTA1) controls a current source (MN1) which supplies an outpu t current (IOUTN). A current-voltage converter (R1) is connected between the node (K1) and the current source (MN1), and a voltage-current converter (R2) is connected between the current source (MN1) and ground (VSS).

公开(公告)号：DE10125366A1

公开(公告)日：2002-12-12

申请号：DE10125366

申请日：2001-05-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER ,  SCHUMACHER OTTO

IPC: H03G1/00 ,  H03G3/00 ,  H03G3/30 ,  H03G3/20

Abstract: The invention relates to a VGA stage having a novel circuit configuration for amplifying/attenuating a differential input signal which is transmitted via a transmission line (H). The VGA stage comprises an operational amplifier (OPV 1 , OPV 2 ), which is connected as shunt feedback, for amplifying the input signal; a string of resistors (R 01 , R 01' ) for attenuating the signal; and a control device ( 2 ) for switching the string of resistors (R 01 , R 01' ).

公开(公告)号：DE10125023A1

公开(公告)日：2002-12-12

申请号：DE10125023

申请日：2001-05-22

Applicant: INFINEON TECHNOLOGIES AG

Inventor： GREGORIUS PETER ,  HANNEBERG ARMIN

IPC: H04L25/08 ,  H04L25/20 ,  H04L25/06

Abstract: The invention relates to a transmitter for transmission of digital data via a transmission line ( 10 ), comprising a current-driving digital/analogue converter ( 1 ) which is arranged at the input of the transmitter; a current-operated form filter ( 2 ) for forming the current pulses which are supplied from the digital/analogue converter; a line driver ( 5 ) which carries out current/voltage conversion; and a circuit for offset compensation ( 6 ), which is arranged in a feedback path ( 11 ). In order to improve the quality of the pulses which are transmitted at the output of the transmitter, the invention proposes that the internal signal processing of the transmitter be carried out on a current basis.