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    MEMORY DEVICE HAVING PLURAL MEMORY CELLS
    11.
    发明专利
    MEMORY DEVICE HAVING PLURAL MEMORY CELLS 失效

    公开(公告)号：JP2000156091A

    公开(公告)日：2000-06-06

    申请号：JP32163899

    申请日：1999-11-11

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： ROEHR THOMAS ,  HOENIGSCHMID HEINZ ,  BRAUN GEORG

    IPC: G11C14/00 ,  G11C11/22

    Abstract: PROBLEM TO BE SOLVED: To reduce remarkably a time for reading out by connecting respectively one short circuit element to one side bit line of two pairs of bit line, applying a reference signal to a sense amplifier through a first pair of bit line, simultaneously, applying a read-out signal to the sense amplifier through a second pair of bit line. SOLUTION: In a short circuit element SG, being not adjacent bit lines, but every other bit lines are connected mutually. This way is indicated by a bit line BL , BL or bBL , bBL , further, in this case, two control lines INIT , INIT are not used for pre-charge, but used for short-circuiting two bit lines BL , BL or bBL , bBL . Active memory cells L and a reference cell R are arranged comparatively densely in the same block as a memory cell field by arranging utilized pairs of bit line in parallel.

    ERROR DETECTION AND CORRECTION METHOD AND APPARATUS IN A MAGNETO-RESISTIVE RANDOM ACCESS MEMORY
    16.
    发明申请
    ERROR DETECTION AND CORRECTION METHOD AND APPARATUS IN A MAGNETO-RESISTIVE RANDOM ACCESS MEMORY 审中-公开
    磁阻随机访问存储器中的错误检测和校正方法和装置

    公开(公告)号：WO2004112048A3

    公开(公告)日：2005-04-07

    申请号：PCT/EP2004006019

    申请日：2004-06-03

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM ,  DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

    Inventor： DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

    IPC: G06F11/10 ,  G11C7/24 ,  G11C11/406 ,  G11C29/00 ,  G11C11/15

    CPC classification number: G11C7/24 ,  G06F11/106 ,  G11C11/406

    Abstract: The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.

    Abstract translation: 本发明涉及一种用于减少磁阻随机存取存储器（MRAM）中的数据错误的方法和装置。 根据所公开的方法，将数据位和相关联的纠错码（ECC）校验位存储到存储区域中。 此后，读出数据位和ECC校验位，并检测和校正任何错误。 然后基于计数开始数据刷新，然后通过访问存储的数据位和相关联的ECC校验位来刷新存储在存储区域中的相关ECC校验位，并且最终通过检查，校正和恢复数据位 并将ECC校验位存储到存储区域。

    FUSE CONCEPT AND METHOD OF OPERATION
    17.
    发明申请
    FUSE CONCEPT AND METHOD OF OPERATION 审中-公开
    保险丝的概念和操作方法

    公开(公告)号：WO03071554A2

    公开(公告)日：2003-08-28

    申请号：PCT/EP0301630

    申请日：2003-02-18

    Applicant: INFINEON TECHNOLOGIES AG

    Inventor： HOENIGSCHMID HEINZ ,  VIEHMANN HEINRICH

    IPC: G11C29/04 ,  G11C17/14 ,  G11C29/00 ,  G11C29/44

    CPC classification number: G11C11/16 ,  G11C17/14 ,  G11C29/72 ,  G11C29/789

    Abstract: It is difficult to fabricate a semiconductor memory device without any faulty memory storage cells. One solution is to produce more storage cells than needed on a device and faulty storage cells are replaced by the redundant storage cells. This solution requires that the addresses of the faulty storage cells, along with the replacement storage cells, be saved in a memory. The present invention teaches the use of non-volatile memory cells, particularly magnetoresistive random access memory (MRAM) cells, to store the addresses. Non-volatile memory cells can effectively replace the laser fuses currently used and also provides an advantage in the elimination of the laser fuse-burning step during the fabrication of the device.

    Abstract translation: 难以制造半导体存储器件而没有任何错误的存储器存储单元。 一个解决方案是生产比设备上所需的更多的存储单元，并且冗余存储单元被替换为故障存储单元。 该解决方案要求将故障存储单元的地址与替换存储单元一起保存在存储器中。 本发明教导了使用非易失性存储单元，特别是磁阻随机存取存储器（MRAM）单元来存储地址。 非易失性存储单元可以有效地替代当前使用的激光熔丝，并且还在设备制造期间消除激光熔丝烧制步骤的优点。

    DRAM WITH BIT LINES IN TWO METALLISED SHEETS
    19.
    发明申请
    DRAM WITH BIT LINES IN TWO METALLISED SHEETS 审中-公开
    在两个金属与DRAM位线

    公开(公告)号：WO0127974A3

    公开(公告)日：2001-10-18

    申请号：PCT/EP0009739

    申请日：2000-10-05

    Applicant: INFINEON TECHNOLOGIES AG ,  HOENIGSCHMID HEINZ ,  BRAUN GEORG

    Inventor： HOENIGSCHMID HEINZ ,  BRAUN GEORG

    IPC: G11C5/10 ,  H01L21/8242 ,  H01L27/108

    CPC classification number: H01L27/10885 ,  G11C5/10 ,  H01L27/10811 ,  H01L27/10814

    Abstract: The invention relates to a memory device comprising numerous memory cells, each cell comprising at least one selection transistor and one stacked capacitor and being driven via word (3) and bit lines (14, 16). Said memory device is characterised in that the bit lines (14, 16) are led through two metallised sheets and in that the stacked capacitors (7, 8, 9) of the memory cells are located between these metallised sheets.

    Abstract translation: 根据本发明，提供了一种具有多个存储器单元的存储器装置的每一个包括至少一个选择晶体管和一个叠置电容器和经由字（3） - 和位线（14，16）是可控的。 根据本发明的存储系统的特征在于：（14，16）在两个金属化被引导所述位线和所述层叠电容器（7，8，9）的金属化平面之间的存储器单元的布置。

    20.
    发明专利
    未知

    公开(公告)号：DE602004021187D1

    公开(公告)日：2009-07-02

    申请号：DE602004021187

    申请日：2004-06-03

    Applicant: INFINEON TECHNOLOGIES AG ,  IBM

    Inventor： DEBROSSE JOHN ,  HOENIGSCHMID HEINZ ,  LEUSCHNER RAINER ,  MUELLER GERHARD

    IPC: G11C29/00 ,  G06F11/10 ,  G11C7/24 ,  G11C11/15 ,  G11C11/406

    Abstract: The present invention relates to a method and apparatus for reducing data errors in a magneto-resistive random access memory (MRAM). According to the disclosed method, data bits and associated error correction code (ECC) check bits are stored into a storage area. Thereafter, the data bits and ECC check bits are read out and any errors are detected and corrected. A data refresh is then initiated based on a count and data bits and associated ECC check bits stored in the storage area are then refreshed by accessing the stored data bits and the associated ECC check bits, and ultimately by checking, correcting and restoring the data bits and the ECC check bits to the storage area.

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